UPD78F1201MC-CAB-AX Renesas Electronics America, UPD78F1201MC-CAB-AX Datasheet - Page 468

• Manufacturer Part Number: UPD78F1201MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1201MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remark
466
During
operation
Operation
stop
TAUS stop
n = 01
m = 02 to 07
The TT00 (master) and TTn (slave 1) bits are set to 1 at
the same time.
Set values of the TDR00 and TDRn registers can be
changed after INTTM00 of the master channel is
generated.
The TCR00 and TCRn registers can always be read.
Set values of the TROn and TROm bits can be
changed.
The TOEn and TOEm bits are cleared to 0 and values
are set to TOn and TOm.
To hold the TOn and TOm pin output levels
When holding the TOn and TOm pin output levels is not
necessary
The TAU0EN and TAUOPEN bits of the PER2 register
are cleared to 0.
Figure 7-71. Operation Procedure of Linked Real-Time Output Function (Type 2) (2/2)
The TT00 and TTn bits automatically return to 0
because they are trigger bits.
Clears the TOn and TOm bits to 0 after the values to
be held are set to the port register.
Switches the port mode register to input mode.
Software Operation
CHAPTER 7 INVERTER CONTROL FUNCTIONS
User’s Manual U19678EJ1V1UD
The TOn and TOm pin output levels go into Hi-Z output
state.
The counter (TCRn) of the master channel counts down.
When the count value reaches TCR00 = 0000H, the value
of TDR00 is loaded to TCR00 again and the count
operation is continued.
INTTM00 is generated.
The counter (TCRn) of the slave channel 1 counts down
every time an INTTM00 signal of the master channel is
detected. When the count value reaches TCRn = 0000H,
the value of TDRn is loaded to TCRn again and the count
operation is continued.
INTTMn is generated. After that, the above operation is
repeated. The set value of TROm of the slave channels 2
to 7 (real-time output channel) is output from TOm at the
INTTMn output timing.
TE00, TEn = 0, and count operation stops.
The set values of TOn and TOm initialize the outputs of
TOn and TOm.
The TOn and TOm pin output levels are held by port
function.
Power-off status
TCR00 and TCRn hold count value and stops.
The TOn and TOm output is not initialized but holds
current status.
All circuits are initialized and SFR of each channel is also
initialized.
(The TOn and TOm bits are cleared to 0 and the TOn
and TOm pins are set to port mode.)
Hardware Status
By detecting TCR00 = 0000H,
By detecting TCRn = 0000H,