UPD78F1201MC-CAB-AX Renesas Electronics America, UPD78F1201MC-CAB-AX Datasheet - Page 256

• Manufacturer Part Number: UPD78F1201MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1201MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.6.5 CPU clock status transition diagram
Note
Remark
254
Internal high-speed oscillation:
Oscillatable
X1 oscillation/EXCLK input:
Oscillatable
XT1 oscillation: Oscillatable
DSC oscillation: Operating
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input:
Cannot be selected by CPU
XT1 oscillation:
Cannot be selected by CPU
DSC oscillation: Operating
Figure 5-15 and Figure 5-16 shows the CPU clock status transition diagram of this product.
After reset release, operation at 4 MHz (8 MHz/2) is started, because f
setting the system clock control register (CKC) to 09H.
DSC: 40 MHz internal high-speed oscillation clock
Internal high-speed oscillation:
Oscillatable
X1 oscillation/EXCLK input:
Oscillatable
XT1 oscillation: Operating
DSC oscillation: Stops
(G)
DSC oscillation
Figure 5-15. CPU Clock Status Transition Diagram (78K0R/IC3, ID3, IE3)
→ HALT
(K)
CPU:
XT1 oscillation
→ HALT
(J)
CPU:
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation: Selectable by CPU
DSC oscillation: Selectable by CPU
DSC oscillation
Operating with
CPU:
(D)
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation: Operating
DSC oscillation: Stops
Operating with
XT1 oscillation
CPU:
CHAPTER 5 CLOCK GENERATOR
Internal high-speed
oscillation: Selectable by CPU
X1 oscillation/EXCLK input:
Operating
XT1 oscillation:
Selectable by CPU
DSC oscillation: Stops
User’s Manual U19678EJ1V1UD
(A)
(B)
(C)
with X1 oscillation or
with internal high-
speed oscillation
Reset release
CPU: Operating
CPU: Operating
Power ON
EXCLK input
(F)
oscillation/EXCLK
input → HALT
Note
CPU: X1
Internal high-speed
oscillation: Oscillatable
X1 oscillation/EXCLK input:
Operating
XT1 oscillation: Oscillatable
DSC oscillation: Stops
Internal high-speed oscillation: Woken up
X1 oscillation/EXCLK input: Stops (input port mode)
XT1 oscillation: Stops (input port mode)
DSC oscillation: Stops
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input: Stops (input port mode)
XT1 oscillation: Stops (input port mode)
DSC oscillation: Stops
(H)
CLK
CPU: Internal high-
CPU: Internal high-
(E)
oscillation/EXCLK
speed oscillation
speed oscillation
(I)
input → STOP
= f
→ STOP
→ HALT
CPU: X1
V
V
V
DD
DD
DD
IH
/2 has been selected by
< 1.61 V±0.09 V
≥ 1.61 V±0.09 V
≥ 2.7 V
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input:
Stops
XT1 oscillation: Oscillatable
DSC oscillation: Stops
Internal high-speed oscillation:
Operating
X1 oscillation/EXCLK input:
Oscillatable
XT1 oscillation: Oscillatable
DSC oscillation: Stops
Internal high-speed
oscillation: Stops
X1 oscillation/EXCLK
input: Stops
XT1 oscillation: Oscillatable
DSC oscillation: Stops