UPD78F1201MC-CAB-AX Renesas Electronics America, UPD78F1201MC-CAB-AX Datasheet - Page 762

• Manufacturer Part Number: UPD78F1201MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1201MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.1 Functions of Serial Interface IICA
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Serial interface IICA has the following three modes.
(1) Operation stop mode
(2) I
(3) Wakeup mode
Figure 14-1 shows a block diagram of serial interface IICA.
Remark
This mode is used when serial transfers are not performed. It can therefore be used to reduce power
consumption.
This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCL0) line and a
serial data bus (SDA0) line.
This mode complies with the I
“transfer direction specification”, “data”, and “stop condition” data to the slave device, via the serial data bus.
The slave device automatically detects these received status and data by hardware. This function can simplify
the part of application program that controls the I
Since the SCL0 and SDA0 pins are used for open drain outputs, IICA requires pull-up resistors for the serial
clock line and the serial data bus line.
The STOP mode can be released by generating an interrupt request signal (INTIICA) when an extension code
from the master device or a local address has been received while in STOP mode. This can be set by using
the WUP bit of IICA control register 1 (IICCTL1).
2
C bus mode (multimaster supported)
Serial interface IICA is only mounted in the 48-pin products of the 78K0R/IC3, 78K0R/ID3, and
78K0R/IE3.
CHAPTER 14 SERIAL INTERFACE IICA
2
C bus format and the master device can generated “start condition”, “address”,
User’s Manual U19678EJ1V1UD
2
C bus.