UPD78F1201MC-CAB-AX Renesas Electronics America, UPD78F1201MC-CAB-AX Datasheet - Page 408

• Manufacturer Part Number: UPD78F1201MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1201MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.5.4 Operation as triangular wave PWM output function
When multiple triangular wave modulation PWMs are output for a period, the triangular wave modulation PWM output
can be added by adding a slave channel.
loads the value of TDR00 again at the same timing. Similar operation is continued hereafter.
status of the slave channel and the second period as an up status of the slave channel.
set, because up and down statuses are output.
an up status.
Hereafter, counting up and counting down is switched in accordance with the operation of the master channel.
INTTMm is output when TCRm becomes 0000H.
an inactive level when TCRm generates INTTMm while counting up.
the master channel. Similar operation is continued hereafter.
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Multiple channels can be used in combination to output a triangular wave modulation PWM for motor control.
The period is set by the master channel and a triangular wave modulation PWM is output by the slave channel.
The output pulse period and duty factor can be calculated by the following expression.
The master channel operates in the interval timer mode and counts the periods.
TCR00 loads the value of TDR00 at the first count clock, after the channel start trigger bit (TS00) is set to 1.
Afterward, TCR00 counts down along with the count clock.
When TCR00 has become 0000H, INTTM00 is output and TO00 is toggled upon the next count clock. TCR00
A carrier period is generated in two periods of the master channel count.
The count operation of the slave channel is controlled by defining the first period of the master channel as a down
TO00 of the master channel outputs up and down statuses.
TO00 of the TO0 register must be manipulated while TOE00 of the TOE0 register is 0 and the default level must be
TO00 of TO0 is set to 1 when MD000 of the TMR00 register is 0, and TO00 is set to 0 when MD000 is 1.
By setting the default level, a high level is output from TO00 during a down status and a low level is output during
TCRm of the slave channel operates in the up and down count mode, and counts the duty.
TCRm loads the value of TDRm at the first count clock, after the channel start trigger bit (TSm) is set to 1.
The TOm output becomes an active level when TCRm generates INTTMm while counting down, and it becomes
TCRm loads the value of TDRm again when INTTM00 is generated in an up status (crest of a triangular wave) of
Remark m = 02 to 07
Remark Although the duty factor exceeds 0% if the set value of TDRm (slave) > {set value of TDR00 (master)
Pulse period (down/up) = {Set value of TDR00 (master) + 1} × 2 × Count clock period
Duty factor [%] = {Set value of TDR00 (master) + 1 − Set value of TDRm (slave)}/{Set value of TDR00
(master) + 1} × 100
0% output:
100% output: Set value of TDRm (slave) = 0000H
+ 1}, it is summarized into 0% output.
Set value of TDRm (slave) ≥ {Set value of TDR00 (master) + 1}
CHAPTER 7 INVERTER CONTROL FUNCTIONS
User’s Manual U19678EJ1V1UD