UPD78F1201MC-CAB-AX Renesas Electronics America, UPD78F1201MC-CAB-AX Datasheet - Page 771

• Manufacturer Part Number: UPD78F1201MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1201MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Notes 1. The signal of this bit is invalid while IICE0 is 0. Set this bit during that period.
ACKE
If WUP of the IICCTL1 register is 1, no stop condition interrupt will be generated even if SPIE = 1.
Condition for clearing (SPIE = 0)
• Cleared by instruction
• Reset
An interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of
this bit. The setting of this bit is valid when the address transfer is completed. When in master mode, a wait is
inserted at the falling edge of the ninth clock during address transfers. For a slave device that has received a local
address, a wait is inserted at the falling edge of the ninth clock after an acknowledge (ACK) is issued. However,
when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock.
Condition for clearing (WTIM = 0)
• Cleared by instruction
• Reset
Condition for clearing (ACKE = 0)
• Cleared by instruction
• Reset
WTIM
SPIE
0
1
0
1
0
1
Notes 1, 2
Note 1
Note 1
2. The set value is invalid during address transfer and if the code is not an extension code.
When the device serves as a slave and the addresses match, an acknowledgment is generated
regardless of the set value.
Disable
Enable
Interrupt request is generated at the eighth clock’s falling edge.
Master mode: After output of eight clocks, clock output is set to low level and wait is set.
Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device.
Interrupt request is generated at the ninth clock’s falling edge.
Master mode: After output of nine clocks, clock output is set to low level and wait is set.
Slave mode: After input of nine clocks, the clock is set to low level and wait is set for master device.
Disable acknowledgment.
Enable acknowledgment. During the ninth clock period, the SDA0 line is set to low level.
Figure 14-6. Format of IICA Control Register 0 (IICCTL0) (2/4)
Enable/disable generation of interrupt request when stop condition is detected
CHAPTER 14 SERIAL INTERFACE IICA
User’s Manual U19678EJ1V1UD
Control of wait and interrupt request generation
Acknowledgment control
Condition for setting (SPIE = 1)
• Set by instruction
Condition for setting (WTIM = 1)
• Set by instruction
Condition for setting (ACKE = 1)
• Set by instruction
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