UPD78F1201MC-CAB-AX Renesas Electronics America, UPD78F1201MC-CAB-AX Datasheet - Page 634

• Manufacturer Part Number: UPD78F1201MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1201MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

632
Address: F0060H
(15) Noise filter enable register 0 (NFEN0)
Symbol
NFEN0
Caution Be sure to clear bits 7 to 5 to “0”.
Caution Be sure to clear bits 7 to 3, and 1 to “0”.
Notes
Remark The presence or absence of channel 0, 1 and 8 to 11 of timer I/O pins in each timer array unit
NFEN0 register is used to set whether the noise filter can be used for the input signal from the serial data
input pin to each channel.
Disable the noise filter of the pin used for CSI or simplified I
bit of this register to 0.
Enable the noise filter of the pin used for UART communication, by setting the corresponding bit of this
register to 1.
When the noise filter is enabled, Operation clock (f
NFEN0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears NFEN0 register to 00H.
Set SNFEN10 bit to 1 to use the R
Clear SNFEN10 bit to 0 to use the alternate pins other than RxD1 pin or port function.
Set SNFEN00 bit to 1 to use the R
Clear SNFEN00 bit to 0 to use the alternate pins other than RxD0 pin or port function.
SNFEN10
SNFEN00
1.
2.
channel depends on the product. For details, see Table 6-1 Timer I/O Pins Included in Each Product
or Tables 6-3 to 6-5 I/O Pins That Can Be Selected for Channels 0, 1, and 8 to 11. For products that
do not provide timer I/O pins for channels 0, 1, and 8 to 11, only the P52/SLTI/SLTO pin can be
selected as a timer I/O pin.
0
1
0
1
7
0
After reset: 00H
ISC2 to ISC4 bits are not provided in the 78K0R/IB3. In the 78K0R/IB3, these bits are fixed to 0.
78K0R/IE3: P17/TI09
Figure 13-18. Format of Noise Filter Enable Register 0 (NFEN0)
Noise filter OFF
Noise filter ON
Noise filter OFF
Noise filter ON
6
0
R/W
78K0R/IB3, 78K0R/IC3, 78K0R/ID3
78K0R/IE3
78K0R/IB3
78K0R/IC3(38-pin)
78K0R/IC3(44-pin, 48pin), 78K0R/ID3, 78K0R/IE3 RxD0/SI00/TI10/P74 pin
CHAPTER 13 SERIAL ARRAY UNIT
X
X
5
0
D1 pin.
D0 pin.
User’s Manual U19678EJ1V1UD
Use of noise filter of the following pin
Use of noise filter of the following pin
MCK
4
0
) is synchronized with 2-clock match detection.
2
C communication, by clearing the corresponding
3
0
RxD1/SDA10/SI10/INTP1/TI09/P31 pin
RxD1/SDA10/SI10/INTP1/P31 pin
SNFEN10
2
RxD0/TI03/TO03/P11 pin
RxD0/INTP6/P72 pin
1
0
SNFEN00
0