UPD78F1201MC-CAB-AX Renesas Electronics America, UPD78F1201MC-CAB-AX Datasheet - Page 789

• Manufacturer Part Number: UPD78F1201MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1201MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(IICCTL0).
to the IICA shift register (IICA), and the transmitting side cancels the wait state when data is written to IICA.
Transfer lines
(2) When master and slave devices both have a nine-clock wait
Remark
A wait may be automatically generated depending on the setting of bit 3 (WTIM) of IICA control register 0
Normally, the receiving side cancels the wait state when bit 5 (WREL) of IICCTL0 is set to 1 or when FFH is written
The master device can also cancel the wait state via either of the following methods.
• By setting bit 1 (STT) of IICCTL0 to 1
• By setting bit 0 (SPT) of IICCTL0 to 1
Master
Slave
(master transmits, slave receives, and ACKE = 1)
ACKE:
WREL: Bit 5 of IICA control register 0 (IICCTL0)
ACKE
SDA0
SCL0
SCL0
SCL0
IICA
IICA
Bit 2 of IICA control register 0 (IICCTL0)
H
Generate according to previously set ACKE value
D2
6
6
Master and slave both wait
after output of ninth clock
D1
7
7
CHAPTER 14 SERIAL INTERFACE IICA
D0
8
8
User’s Manual U19678EJ1V1UD
Figure 14-20. Wait (2/2)
ACK
9
9
Wait from
master and
slave
Wait from slave
IICA data write (cancel wait)
1
D7
1
FFH is written to IICA or WREL is set to 1
D6
2
2
D5
3
3
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