UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 189

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

AD15 to AD0
Note This idle state (TI) does not depend on the BCC register settings.
Remarks 1. See Table 2-2 for the pin statuses in the bus hold mode.
Remarks 1. TASW (address setup wait): Image of high-level width of T1 state expanded.
A21 to A16
CLKOUT
AD15 to AD0
HLDRQ
HLDAK
A21 to A16
ASTB
CLKOUT
RD
ASTB
WAIT
2. The broken lines indicate high impedance.
2. TAHW (address hold wait): Image of low-level width of T1 state expanded.
3. The broken lines indicate high impedance.
RD
Figure 5-8. Multiplexed Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access)
Figure 5-9. Address Wait Timing (Bus Size: 16 Bits, 16-Bit Access)
T1
A1
T1
A1
T2
A1
D1
A1
T2
D1
CHAPTER 5 BUS CONTROL FUNCTION
T3
Preliminary User’s Manual U18953EJ1V0UD
Undefined
Undefined
TI
Note
AD15 to AD0
A21 to A16
CLKOUT
TH
ASTB
WAIT
RD
TH
TASW
TH
TH
T1
A1
Undefined
Undefined
TI
A1
Note
TAHW
A2
T1
T2
D1
D2
T2
A2
T3
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