UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 635

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(4) DMA addressing control registers 0 to 3 (DADC0 to DADC3)
Cautions 1. Be sure to clear bits 15, 13 to 8, and 3 to 0 of the DADCn register to 0.
The DADC0 to DADC3 registers are 16-bit registers that control the DMA transfer mode for DMA channel n (n
= 0 to 3).
These registers can be read or written in 16-bit units.
Reset sets these registers to 0000H.
2. Set the DADCn register at the following timing when DMA transfer is disabled (DCHCn.Enn
3. The DS0 bit specifies the size of the transfer data, and does not control bus sizing. If 8-bit
4. If the transfer data size is set to 16 bits (DS0 bit = 1), transfer cannot be started from an
5. If DMA transfer is executed on an on-chip peripheral I/O register (as the transfer source or
(n = 0 to 3)
bit = 0).
data (DS0 bit = 0) is set, therefore, the lower data bus is not always used.
odd address. Transfer is always started from an address with the first bit of the lower
address aligned to 0.
destination), be sure to specify the same transfer size as the register size. For example, to
execute DMA transfer on an 8-bit register, be sure to specify 8-bit transfer.
DADCn
• Period from after reset to start of first DMA transfer
• Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer
• Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next
After reset:
DMA transfer
SAD1
DAD1
SAD1
DS0
0000H
15
0
1
0
0
1
1
0
0
1
1
0
7
CHAPTER 18 DMA FUNCTION (DMA CONTROLLER)
8 bits
16 bits
SAD0
DAD0
SAD0
DS0
R/W
14
0
1
0
1
0
1
0
1
6
Preliminary User’s Manual U18953EJ1V0UD
Increment
Decrement
Fixed
Setting prohibited
Increment
Decrement
Fixed
Setting prohibited
Address:
DAD1
13
Setting of count direction of the transfer source address
0
5
Setting of count direction of the destination address
DADC0 FFFFF0D0H, DADC1 FFFFF0D2H,
DADC2 FFFFF0D4H, DADC3 FFFFF0D6H
DAD0
Setting of transfer data size
12
0
4
11
0
3
0
10
0
0
2
9
0
1
0
8
0
0
0
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