UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 224
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UPD70F3737GC-UEU-AX
Manufacturer Part Number
UPD70F3737GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3737GC-UEU-AX.pdf
(861 pages)
Specifications of UPD70F3737GC-UEU-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
84
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
8K x 8
Program Memory Size
128KB (128K x 8)
Data Converters
A/D 12x10b, D/A 2x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3737GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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with the count clock, and the counter starts counting. At this time, the output of the TOPn0 pin is inverted. Additionally,
the set value of the TPnCCR0 register is transferred to the CCR0 buffer register.
cleared to 0000H, the output of the TOPn0 pin is inverted, and a compare match interrupt request signal
(INTTPnCC0) is generated.
224
TPnCTL0
TPnCTL1
When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is
The interval can be calculated by the following expression.
Interval = (Set value of TPnCCR0 register + 1) × Count clock cycle
Remark
Note This bit can be set to 1 only when the interrupt request signals (INTTPnCC0 and INTTPnCC1) are
(a) TMPn control register 0 (TPnCTL0)
(b) TMPn control register 1 (TPnCTL1)
masked by the interrupt mask flags (TPnCCMK0 and TPnCCMK1) and timer output (TOPn1) is
performed at the same time. However, set the TPnCCR0 and TPnCCR1 registers to the same value (see
7.5.1 (2) (d) Operation of TPnCCR1 register).
TPnCE
n = 0 to 5
0/1
0
TPnEST
Figure 7-4. Register Setting for Interval Timer Mode Operation (1/2)
0
0
TPnEEE
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
0/1
0
Note
Preliminary User’s Manual U18953EJ1V0UD
0
0
0
0
TPnCKS2 TPnCKS1 TPnCKS0
TPnMD2 TPnMD1 TPnMD0
0/1
0
0/1
0
0/1
0
Select count clock
0: Stop counting
1: Enable counting
0, 0, 0:
Interval timer mode
0: Operate on count
1: Count with external
clock selected by
TPnCKS0 to TPnCKS2 bits
event count input signal
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