UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 797
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3737GC-UEU-AX
Manufacturer Part Number
UPD70F3737GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3737GC-UEU-AX.pdf
(861 pages)
Specifications of UPD70F3737GC-UEU-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
84
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
8K x 8
Program Memory Size
128KB (128K x 8)
Data Converters
A/D 12x10b, D/A 2x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3737GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Main Clock Oscillator Characteristics
(T
Notes 1. The oscillation frequency shown above indicates only oscillator characteristics. Use the V850ES/JG3-L so
Cautions 1. When using the main clock oscillator, wire as follows in the area enclosed by the broken lines in
Ceramic
resonator/
Crystal
resonator
Resonator
A
= −40 to +85°C, V
2. Time required from start of oscillation until the resonator stabilizes.
3. The oscillation stabilization time differs depending on the set value of the option byte. For details, see
4. The value varies depending on the setting of the OSTS register.
5. Time required to set up the regulator and flash memory. Secure the setup time using the OSTS register.
6. Time required to set up the regulator, flash memory, and PLL. Secure the setup time using the OSTS
2. When the main clock is stopped and the device is operating on the subclock, wait until the
that the internal operation conditions do not exceed the ratings shown in AC Characteristics and DC
Characteristics.
CHAPTER 27 OPTION BYTE.
register.
the above figure to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as V
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
oscillation stabilization time has been secured by the program before switching back to the
main clock.
X1
Circuit Example
DD
= EV
DD
CHAPTER 30 ELECTRICAL SPECIFICATIONS (TARGET)
X2
= AV
REF0
Oscillation
frequency (f
Oscillation
stabilization
time
= AV
Preliminary User’s Manual U18953EJ1V0UD
Parameter
Note 2
REF1
= 2.2 to 3.6 V, V
X
)
Note 1
Clock through mode
PLL mode
After reset is released
After STOP
mode is
released
After
IDLE2
mode is
released
SS
Conditions
= EV
Clock through
mode
PLL mode
Clock through
mode
PLL mode
SS
= AV
SS
= 0 V)
350
800
Note 3
MIN.
1
1
2.5
2.5
Note 5
Note 6
Note 5
Note 6
Note 3
Note 4
Note 4
Note 4
Note 4
TYP.
SS
MAX.
.
10
5
MHz
MHz
Unit
ms
ms
μ
μ
s
797
s
s
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