UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 674
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UPD70F3737GC-UEU-AX
Manufacturer Part Number
UPD70F3737GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3737GC-UEU-AX.pdf
(861 pages)
Specifications of UPD70F3737GC-UEU-AX
Package / Case
*
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
84
Core Processor
RISC
Program Memory Type
FLASH
Ram Size
8K x 8
Program Memory Size
128KB (128K x 8)
Data Converters
A/D 12x10b, D/A 2x8b
Oscillator Type
Internal
Peripherals
DMA, LVD, PWM, WDT
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3737GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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19.3.7 ID flag
disabling of interrupt request signals. An interrupt disable flag (ID) is assigned to the PSW.
19.3.8 Watchdog timer mode register 2 (WDTM2)
TIMER 2).
674
This flag controls the maskable interrupt’s operating state, and stores control information regarding enabling or
Reset sets this flag to 00000020H.
This register can be read or written in 8-bit units (for details, see CHAPTER 11 FUNCTIONS OF WATCHDOG
Reset sets this register to 67H.
Note Interrupt disable flag (ID) function
After reset:
PSW
This bit is set to 1 by the DI instruction and cleared to 0 by the EI instruction. Its value is also modified by
the RETI instruction or LDSR instruction when referencing the PSW.
Non-maskable interrupt request signals and exceptions are acknowledged regardless of this flag. When
a maskable interrupt request signal is acknowledged, the ID flag is automatically set to 1 by hardware.
The interrupt request signal generated during the acknowledgment disabled period (ID flag = 1) is
acknowledged when the xxICn.xxIFn bit is set to 1, and the ID flag is cleared to 0.
WDTM2
00000020H
After reset: 67H
ID
0
1
WDM21
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
0
0
1
0
Maskable interrupt request signal acknowledgment enabled
Maskable interrupt request signal acknowledgment disabled (pending)
WDM20
WDM21
R/W
0
1
×
Preliminary User’s Manual U18953EJ1V0UD
0
Address: FFFFF6D0H
Stops operation
Non-maskable interrupt request mode
Reset mode (initial-value)
WDM20
Specification of maskable interrupt servicing
Selection of watchdog timer operation mode
0
0
NP EP
0
ID SAT CY OV
0
Note
0
S
Z
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