UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 783

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

29.2 Debugging Without Using DCU
(RXDA0 and TXDA0), pins for CSIB0 (SIB0, SOB0, SCKB0, and HS (PMC0)), or pins for CSIB3 (SIB3, SOB3, SCKB3,
and HS (PMC0)) as debug interfaces, without using the DCU.
29.2.1 Circuit connection examples
Figure 29-3. Circuit Connection Example When UARTA0/CSIB0/CSIB3 Is Used for Communication Interface
The following describes how to implement an on-chip debug function using MINICUBE2 with pins for UARTA0
Notes 1. Connect TXDA0/SOB0/SOB3 (transmit side) of the V850ES/JG3-L to RXD/SI (receive side) of the
Remark See Table 29-3 for pins used when UARTA0, CSIB0, or CSIB3 is used for communication interface.
2. This pin may be used to supply a clock from MINICUBE2 during flash memory programming. For
3. The V850ES/JG3-L-side pin connected to this pin (FLMD0, FLMD1) can be used as an alternate-
4. This connection is designed assuming that the RESET signal is output from the N-ch open-drain
5. The circuit enclosed by a dashed line is designed for flash self programming, which controls the
target connector, and TXD/SO (transmit side) of the target connector to RXDA0/SIB0/SIB3 (receive
side) of the V850ES/JG3-L.
details, see CHAPTER 28 FLASH MEMORY.
function pin other than while the memory is rewritten during a break in debugging, because this pin
is in Hi-Z state.
buffer (output resistance: 100 Ω or less).
FLMD0 pin via ports. Use the port for inputting or outputting the high level. When flash self
programming is not performed, a pull-down resistance for the FLMD0 pin can be within 1 to 10 kΩ.
RESET_IN
RESET_OUT
QB-MINI2
TXD/SO
RXD/SI
FLMD1
FLMD0
CLK
GND
VDD
SCK
Note 1
Note 1
Note 2
Note 3
Note 3
Note 4
HS
CHAPTER 29 ON-CHIP DEBUG FUNCTION
V
DD
Preliminary User’s Manual U18953EJ1V0UD
10
kΩ
1 to 10
1 to 10
kΩ
1 to 10
V
V
DD
DD
kΩ
1
V
kΩ
kΩ
DD
3 to 10
1 to 10
kΩ
10
kΩ
kΩ
V
RESET signal
DD
100
Ω
V
RESET
TXDA0/SOB0/SOB3
V
RXDA0/SIB0/SIB3
SCKB0/SCKB3
HS (PCM0)
FLMD1
FLMD0
Port X
DD
SS
V850ES/JG3-L
Reset circuit
Note 5
783