UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 371

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

TQ0IOC2
TQ0OPT0
(e) TMQ0 I/O control register 2 (TQ0IOC2)
(f) TMQ0 option register 0 (TQ0OPT0)
(g) TMQ0 counter read buffer register (TQ0CNT)
(h) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3)
The value of the 16-bit counter can be read by reading the TQ0CNT register.
These registers function as capture registers or compare registers depending on the setting of the
TQ0OPT0.TQ0CCSm bit.
When the registers function as capture registers, they store the count value of the 16-bit counter when
the valid edge input to the TIQ0m pin is detected.
When the registers function as compare registers and when D
INTTQ0CCm signal is generated when the counter reaches (D
TOQ0m pin is inverted.
Remark
TQ0CCS3
0
0/1
m = 0 to 3
TQ0CCS2
Figure 8-31. Register Setting in Free-Running Timer Mode (3/3)
0/1
0
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
TQ0CCS1
0
0/1
Preliminary User’s Manual U18953EJ1V0UD
TQ0CCS0
0/1
0
TQ0EES1
0/1
0
TQ0EES0 TQ0ETS1 TQ0ETS0
0/1
0
0
0
m
m
is set to the TQ0CCRm register, the
+ 1), and the output signal of the
TQ0OVF
0/1
0
Select valid edge of
external event count input
Overflow flag
Specifies if TQ0CCR0
register functions as
capture or compare register
Specifies if TQ0CCR1
register functions as
capture or compare register
Specifies if TQ0CCR2
register functions as
capture or compare register
Specifies if TQ0CCR3
register functions as
capture or compare register
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