UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 52

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

52
(4) Program status word (PSW)
Remark
31 to 8
7
6
5
4
3
2
1
0
Bit position
PSW
The program status word (PSW) is a collection of flags that indicate the status of the program (result of
instruction execution) and the status of the CPU.
If the contents of a bit of this register are changed by using the LDSR instruction, the new contents are
validated immediately after completion of LDSR instruction execution. However if the ID flag is set to 1,
interrupt requests will not be acknowledged while the LDSR instruction is being executed.
Bits 31 to 8 of this register are reserved for future function expansion (these bits are fixed to 0).
Also read Note on the next page.
31
RFU
NP
EP
ID
SAT
CY
OV
S
Z
Flag name
Note
Note
Note
Reserved field. Fixed to 0.
Indicates that a non-maskable interrupt (NMI) is being serviced. This bit is set to 1 when an
NMI request is acknowledged, disabling multiple interrupts.
Indicates that an exception is being processed. This bit is set to 1 when an exception
occurs. Even if this bit is set, interrupt requests are acknowledged.
Indicates whether a maskable interrupt can be acknowledged.
Indicates that the result of a saturation operation has overflowed and is saturated. Because
this is a cumulative flag, it is set to 1 when the result of a saturation operation instruction is
saturated, and is not cleared to 0 even if the subsequent operation result is not saturated.
Use the LDSR instruction to clear this bit. This flag is neither set to 1 nor cleared to 0 by
execution of an arithmetic operation instruction.
Indicates whether a carry or a borrow occurs as a result of an operation.
Indicates whether an overflow occurs during operation.
Indicates whether the result of an operation is negative.
Indicates whether the result of an operation is 0.
0: NMI is not being serviced.
1: NMI is being serviced.
0: Exception is not being processed.
1: Exception is being processed.
0: Interrupt enabled
1: Interrupt disabled
0: Not saturated
1: Saturated
0: Carry or borrow does not occur.
1: Carry or borrow occurs.
0: Overflow does not occur.
1: Overflow occurs.
0: The result is positive or 0.
1: The result is negative.
0: The result is not 0.
1: The result is 0.
Preliminary User’s Manual U18953EJ1V0UD
RFU
CHAPTER 3 CPU FUNCTION
Meaning
8 7
NP
EP
6
ID
5
SAT
4
CY
3
OV
2
S Z
1
0
Default value
00000020H
(1/2)