UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 270

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

and TOPn1 pins are inverted. When the count value of the 16-bit counter later matches the set value of the
TPnCCRm register, a compare match interrupt request signal (INTTPnCCm) is generated, and the output signal of the
TOPnm pin is inverted.
generates an overflow interrupt request signal (INTTPnOV) at the next clock, is cleared to 0000H, and continues
counting. At this time, the overflow flag (TPnOPT0.TPnOVF bit) is also set to 1. Clear the overflow flag to 0 by
executing the CLR instruction by software.
at that time, and compared with the count value.
270
When the TPnCE bit is set to 1, 16-bit timer/event counter P starts counting, and the output signals of the TOPn0
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
The TPnCCRm register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected
Remark
INTTPnCC0 signal
INTTPnCC1 signal
TPnCCR0 register
TPnCCR1 register
TOPn0 pin output
TOPn1 pin output
INTTPnOV signal
n = 0 to 5
m = 0, 1
16-bit counter
TPnOVF bit
TPnCE bit
Figure 7-29. Basic Timing in Free-Running Timer Mode (Compare Function)
FFFFH
0000H
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
D
10
Preliminary User’s Manual U18953EJ1V0UD
D
00
D
CLR instruction
Cleared to 0 by
10
D
00
D
10
D
00
Cleared to 0 by
CLR instruction
D
11
D
01
Cleared to 0 by
CLR instruction
D
11
D
D
D
01
01
11
CLR instruction
Cleared to 0 by
D
11