UPD70F3737GC-UEU-AX Renesas Electronics America, UPD70F3737GC-UEU-AX Datasheet - Page 581

• Manufacturer Part Number: UPD70F3737GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3737GC-UEU-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 84
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 128KB (128K x 8)
• Data Converters: A/D 12x10b, D/A 2x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.6.6 Wait state
receive data (i.e., is in a wait state).
been canceled for both the master and slave devices, the next data transfer can begin (n = 0 to 2).
A wait state is used to notify the communication partner that a device (master or slave) is preparing to transmit or
Setting the SCL0n pin to low level notifies the communication partner of the wait state. When the wait state has
Transfer lines
Remark
Master
Slave
(a) When master device has a nine-clock wait and slave device has an eight-clock wait
ACKEn
SDA0n
SCL0n
SCL0n
SCL0n
IICn
IICn
n = 0 to 2
(master: transmission, slave: reception, and IICCn.ACKEn bit = 1)
H
D2
6
6
D1
7
7
Preliminary User’s Manual U18953EJ1V0UD
Master returns to high
impedance but slave
is in wait state (low level).
Wait after output
of eighth clock.
Figure 17-13. Wait State (1/2)
D0
8
8
CHAPTER 17 I
Wait state
from slave
9
ACK
2
C BUS
9
FFH is written to IICn register or
IICCn.WRELn bit is set to 1.
Wait after output
of ninth clock.
Wait state
from master
IICn data write (cancel wait state)
D7
1
1
D6
2
2
D5
3
3
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