UPD70F3713GC-8BS-A Renesas Electronics America, UPD70F3713GC-8BS-A Datasheet - Page 252

• Manufacturer Part Number: UPD70F3713GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3713GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

250
(6) TMQn option register 0 (TQnOPT0)
Notes 1. Valid only in TMQ0. Be sure to clear bits 7 to 4 in TMQ1 to 0.
Cautions 1. Rewrite the TQ0CCS3 to TQ0CCS0 bits when the TQ0CE bit = 0. (The same value can be
The TQnOPT0 register is an 8-bit register used to set the capture/compare operation and detect overflow.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
2. Valid only in TMQ1. Be sure to clear bits 2 and 1 of TMQ0 to 0. For details of the TQ1CMS and
2. Be sure to clear bit 3 to “0”.
TQ1CUF bits, see CHAPTER 9 MOTOR CONTROL FUNCTION.
TQnOPT0
(n = 0, 1)
written when the TQ0CE bit = 1.) If rewriting was mistakenly performed, clear (0) the
TQ0CE bit = 0 and then set the bits again.
After reset: 00H
TQ0CCS3
TQ0CCSm
• The TQnOVF bit is set (1) when the 16-bit counter value overflows from FFFFH to
• An overflow interrupt request signal (INTTQnOV) is generated at the same time
• The TQnOVF bit is not cleared to 0 even when the TQnOVF bit or the TQnOPT0
• Before clearing the TQnOVF bit to 0 after generation of the INTTQnOV signal, be
• The TQnOVF bit can be read or written, but the TQnOVF bit cannot be set (1) by
Set (1)
Reset (0)
The TQ0CCSm bit setting is valid only in the free-running timer mode.
0000H in the free-running timer mode or the pulse width measurement mode.
that the TQnOVF bit is set (1). The INTTQnOV signal is not generated in modes
other than the free-running timer mode and the pulse width measurement mode.
register is read when the TQnOVF bit = 1.
sure to confirm (by reading) that the TQnOVF bit is set to 1.
software. Writing 1 has no effect on the TMQn operation.
<7>
0
1
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ)
TQnOVF
Note 1
TQ0CCS2
Compare register selected
Capture register selected (cleared by TQ0CTL0.TQ0CE bit = 0)
R/W
<6>
Note 1
TQ0CCRm register capture/compare selection (m = 0 to 3)
Address: TQ0OPT0 FFFFF5C5H, TQ1OPT0 FFFFF605H
TQ0CCS1
User’s Manual U17716EJ2V0UD
Overflow occurred
0 written to TQnOVF bit or TQnCTL0.TQnCE bit = 0
<5>
Note 1
TQ0CCS0
<4>
Note 1
TMQn overflow flag
3
0
TQ1CMS
<2>
Note 2
TQ1CUF
<1>
Note 2
TQnOVF
<0>