UPD70F3713GC-8BS-A Renesas Electronics America, UPD70F3713GC-8BS-A Datasheet - Page 569

• Manufacturer Part Number: UPD70F3713GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3713GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.4.2 Edge detection
valid edge is one of the following.
The valid edges of the INTP0 to INTP6 pins can be selected by program. The edge that can be selected as the
• Rising edge
• Falling edge
• Both the rising and falling edges
The edge-detected INTP0 to INTP6 signals become interrupt sources.
The valid edge is specified by the INTR0 and INTF0 registers.
(1) External interrupt rising edge specification register 0 (INTR0), external interrupt falling edge
Caution When not using these pins as the INTP0 to INTP6 pins, be sure to clear the INTF0n and INTR0n
Remark
INTF0n
0
0
1
1
specification register 0 (INTF0)
The INTR0 and INTF0 registers are 8-bit registers that specify the trigger mode of the INTP0 to INTP6 pins
and can specify the valid edge independently for each pin (rising edge, falling edge, or both rising and falling
edges).
These registers can be read or written in 8-bit or 1-bit units.
Reset sets these registers to 00H.
Caution When the function is changed from the external interrupt function (alternate function) to the
bits to 00.
For the valid edge specification, see Table 14-3.
INTR0
INTF0
After reset: 00H
After reset: 00H
INTR0n
port mode, an edge may be detected. Therefore, be sure to clear the INTF0n and INTR0n bits
to 00, and then set the port mode.
0
1
0
1
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION
7
0
7
0
No edge detected
Rising edge
Falling edge
Both rising and falling edges
R/W
R/W
INTR06
INTF06
<6>
<6>
Table 14-3. Valid Edge Specification
Address: FFFFFC20H
Address: FFFFFC00H
INTR05
INTF05
User’s Manual U17716EJ2V0UD
<5>
<5>
INTR04
INTF04
<4>
<4>
Valid Edge Specification (n = 0 to 6)
INTR03
INTF03
<3>
<3>
INTR02
INTF02
<2>
<2>
INTR01
INTF01
<1>
<1>
INTR00
INTF00
<0>
<0>
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