UPD70F3713GC-8BS-A Renesas Electronics America, UPD70F3713GC-8BS-A Datasheet - Page 61

• Manufacturer Part Number: UPD70F3713GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3713GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3) System status register
Status flags that indicate the operation status of the overall system are allocated to this register. This register
can be used as SYS or SYS2 via a special register setting.
(a) System status register (SYS)
(b) System status register 2 (SYS2)
If this register is not written in the correct sequence including an access to the PRCMD2 register, data is
not written to the intended register, a protection error occurs, and the PRERR2 flag is set. This register is
cleared by writing “0” to it by an instruction from CPU.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
If this register is not written in the correct sequence including an access to the PRCMD register, data is
not written to the intended register, a protection error occurs, and the PRERR flag is set. This register is
cleared by writing “0” to it by an instruction from CPU.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
SYS2
After reset: 00H
After reset: 00H
SYS
PRERR2
PRERR
0
1
0
0
1
0
Protection error did not occur.
Protection error occurred.
R/W
R/W
Protection error did not occur.
Protection error occurred.
0
0
Address: FFFFF8AAH
Address: FFFFF802H
CHAPTER 3 CPU FUNCTION
User’s Manual U17716EJ2V0UD
0
0
Protection error detection
Protection error detection
0
0
0
0
0
0
0
0
PRERR2
PRERR
<0>
<0>
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