UPD70F3713GC-8BS-A Renesas Electronics America, UPD70F3713GC-8BS-A Datasheet - Page 398

• Manufacturer Part Number: UPD70F3713GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3713GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.4.4
has a buffer register.
396
The following seven registers are provided with a transfer function and used to control a motor. Each of registers
• TQ1CCR0: Register that specifies the cycle of the 16-bit counter (TMQ)
• TQ1CCR1: Register that specifies the duty factor of TOQ1T1 (U) and TOQ1B1 (U)
• TQ1CCR2: Register that specifies the duty factor of TOQ1T2 (V) and TOQ1B2 (V)
• TQ1CCR3: Register that specifies the duty factor of TOQ1T3 (W) and TOQ1B3 (W)
• TQ1OPT1: Register that specifies the culling of interrupts
• TP1CCR0: Register that specifies the A/D conversion start trigger generation timing (TMP1 during tuning
• TP1CCR1: Register that specifies the A/D conversion start trigger generation timing (TMP1 during tuning
The following three rewrite modes are provided in the registers with a transfer function.
• Anytime rewrite mode
• Batch rewrite mode (transfer mode)
• Intermittent batch rewrite mode (transfer culling mode)
This mode is set by setting the TQ1OPT0.TQ1CMS bit to 1. The setting of the TQ1OPT2.TQ1RDE bit is ignored.
In this mode, each compare register is updated independently, and the value of the compare register is updated
as soon as a new value is written to it.
This mode is set by clearing the TQ1CMS bit of TQ1OPT0 to 0, the TQ1OPT1.TQ1ID4 to TQ1OPT1.TQ1ID0 bits
to 00000, and the TQ1OPT2.TQ1RDE bit to 0. When data is written to the TQ1CCR1 register, the seven
registers are transferred to the buffer register all at once at the next transfer timing. Unless the TQ1CCR1
register is rewritten, the transfer operation is not performed even if the other six registers are rewritten.
The transfer timing is the timing of each crest (match between the 16-bit counter value and TQ1CCR0 register
value) and valley (match between the 16-bit counter value and 0001H) regardless of the interrupt.
This mode is set by clearing the TQ1OPT0.TQ1CMS bit to 0 and setting the TQ1OPT2.TQ1RDE bit to 1.
When data is written to the TQ1CCR1 register, the seven registers are transferred to the buffer register all at
once at the next transfer timing. Unless the TQ1CCR1 register is rewritten, the transfer operation is not
performed even if the other six registers are rewritten.
If interrupt culling is specified by the TQ1OPT1 register, the transfer timing is also culled as the interrupts are
culled, and the seven registers are transferred all at once at the culled timing of crest interrupt (match between
the 16-bit counter value and TQ1CCR0 register value) or valley interrupt (match between the 16-bit counter value
and 0001H).
For details of the interrupt culling function, see 9.4.3 Interrupt culling function.
Operation to rewrite register with transfer function
operation)
operation)
CHAPTER 9 MOTOR CONTROL FUNCTION
User’s Manual U17716EJ2V0UD