UPD70F3713GC-8BS-A Renesas Electronics America, UPD70F3713GC-8BS-A Datasheet - Page 295

• Manufacturer Part Number: UPD70F3713GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3713GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from
the TOQ0b pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and
restarted. (The output of the TOQ00 pin is inverted. The TOQ0b pin outputs high level regardless of the status
(high/low) when a trigger occurs.)
after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The
compare match interrupt request signal INTTQ0CCb is generated when the count value of the 16-bit counter matches
the value of the CCRb buffer register.
counter matches the value of the CCRa buffer register and the 16-bit counter is cleared to 0000H.
TQ0CTL0
16-bit timer/event counter Q waits for a trigger when the TQ0CE bit is set to 1. When the trigger is generated, the
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
The compare match interrupt request signal INTTQ0CC0 is generated when the 16-bit counter counts next time
The value set to the TQ0CCRa register is transferred to the CCRa buffer register when the count value of the 16-bit
Only setting the software trigger (TQ0CTL1.TQ0EST bit) to 1 is used as the trigger.
Remark
Active level width = (Set value of TQ0CCRb register) × Count clock cycle
Cycle = (Set value of TQ0CCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TQ0CCRb register)/(Set value of TQ0CCR0 register + 1)
(a) TMQ0 control register 0 (TQ0CTL0)
Note The setting is invalid when the TQ0CTL1.TQ0EEE bit = 1.
a = 0 to 3
b = 1 to 3
TQ0CE
0/1
Figure 7-24. Setting of Registers in External Trigger Pulse Output Mode (1/3)
0
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ)
0
0
User’s Manual U17716EJ2V0UD
0
TQ0CKS2 TQ0CKS1 TQ0CKS0
0/1
0/1
0/1
Select count clock
0: Stop counting
1: Enable counting
Note
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