UPD70F3713GC-8BS-A Renesas Electronics America, UPD70F3713GC-8BS-A Datasheet - Page 561

• Manufacturer Part Number: UPD70F3713GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3713GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
14.3.4 Interrupt control registers (xxICn)
for each maskable interrupt request.
An xxICn register is assigned to each interrupt request signal (maskable interrupt) and sets the control conditions
These registers can be read or written in 8-bit or 1-bit units.
Reset sets these registers to 47H.
Cautions 1. Disable interrupts (DI) to read the xxICn.xxIFn bit. If the xxIFn bit is read while interrupts are
The addresses and bits of the interrupt control registers are as follows.
Note The flag xxlFn is reset automatically by the hardware if an interrupt request signal is acknowledged.
Remark
2. When manipulating the xxICn.xxMKn bit while interrupt requests may occur (including the
xx: Identification name of each peripheral unit (see Table 14-2)
n: Peripheral unit number (see Table 14-2)
xxICn
After reset:
enabled (EI), the correct value may not be read when acknowledging an interrupt and reading
the bit conflict.
state in which interrupts are disabled (DI)), be sure to use a bit manipulation instruction or
use the xxMKn bit of the IMRm register (m = 0 to 3).
xxPRn2
xxMKn
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION
xxIFn
xxIFn
47H
<7>
0
1
0
1
0
0
0
0
1
1
1
1
Interrupt request not issued
Interrupt request issued
Interrupt servicing enabled
Interrupt servicing disabled (pending)
xxPRn1
R/W
xxMKn
<6>
0
0
1
1
0
0
1
1
Address:
xxPRn0
User’s Manual U17716EJ2V0UD
0
0
1
0
1
0
1
0
1
FFFFF110H to FFFFF186H
Specifies level 0 (highest).
Specifies level 1.
Specifies level 2.
Specifies level 3.
Specifies level 4.
Specifies level 5.
Specifies level 6.
Specifies level 7 (lowest).
Interrupt request flag
0
Interrupt mask flag
Interrupt priority specification bit
0
xxPRn2
Note
xxPRn1
xxPRn0
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