UPD70F3713GC-8BS-A Renesas Electronics America, UPD70F3713GC-8BS-A Datasheet - Page 573

• Manufacturer Part Number: UPD70F3713GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3713GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.6 Exception Trap
V850ES/IE2, an illegal opcode trap (ILGOP: Illegal Opcode Trap) is considered as an exception trap.
14.6.1 Illegal opcode definition
and a sub-opcode (bit 16) of 0B. An exception trap is generated when an instruction applicable to this illegal
instruction is executed.
An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the
The illegal instruction has an opcode (bits 10 to 5) of 111111B, a sub-opcode (bits 26 to 23) of 0111B to 1111B,
Caution Since it is possible that this instruction may be assigned to an illegal opcode in the future, it is
(1) Operation
If an exception trap occurs, the CPU performs the following processing, and transfers control to the handler
routine.
<1> Saves the restored PC to DBPC.
<2> Saves the current PSW to DBPSW.
<3> Sets the PSW.NP, PSW.EP, and PSW.ID bits (1).
<4> Sets the handler address (00000060H) corresponding to the exception trap to the PC, and transfers
The processing of the exception trap is shown below.
control.
recommended that it not be used.
×: Arbitrary
15
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CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION
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User’s Manual U17716EJ2V0UD
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31
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27 26
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to
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23 22
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× × × × × ×
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