UPD70F3713GC-8BS-A Renesas Electronics America, UPD70F3713GC-8BS-A Datasheet - Page 589

• Manufacturer Part Number: UPD70F3713GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3713GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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15.5 STOP Mode
15.5.1 Setting and operation status
mode.
functions is stopped.
are retained. The CPU and other on-chip peripheral functions stop operating. The on-chip peripheral functions that
can operate with an external clock continue operating.
than the IDLE mode. The power consumption is therefore minimized with only leakage current flowing if the external
clock is not used.
15.5.2 Releasing STOP mode
unmasked internal interrupt request signal (INTLVI), unmasked internal interrupt request signal from the peripheral
functions operable in the STOP mode (interrupt request signal related to CSIB in the slave mode), or reset signal
(RESET pin input, reset signal generation by low-voltage detection (LVIRES), and reset signal generation by power-
on clear (POCRES)).
time has been secured.
The STOP mode is set by setting (1) the PSMR.PSM0 bit and setting (1) the PSC.STB bit in the normal operation
In the STOP mode, the clock generator stops operation. Clock supply to the CPU and the on-chip peripheral
As a result, program execution is stopped, and the contents of the internal RAM before the STOP mode was set
Table 15-7 shows the operation status in the STOP mode.
Because the STOP mode stops operation of the clock generator, it reduces the power consumption to a level lower
Caution Insert five or more NOP instructions after the instruction that stores data in the PSC register to
The STOP mode is released by an unmasked external interrupt request signal (INTP0 to INTP5 pin input),
After the STOP mode has been released, the normal operation mode is restored after the oscillation stabilization
(1) Releasing STOP mode by unmasked maskable interrupt request signal
The STOP mode is released by an unmasked maskable interrupt request signal, regardless of the priority of
the interrupt request. If the STOP mode is set in an interrupt servicing routine, however, an interrupt request
that is issued later is serviced as follows.
Caution When the PSC.INTM bit is set to 1, the STOP mode cannot be released by an unmasked
(a) If an interrupt request signal with a priority lower than or same as the interrupt request signal currently
(b) If an interrupt request signal with a priority higher than that of the interrupt request signal currently being
being serviced is generated, the STOP mode is released, but the newly generated interrupt request signal
is not acknowledged. The interrupt request signal itself is retained. Therefore, execution starts at the next
instruction after the STOP instruction.
serviced is issued, the STOP mode is released and that interrupt request signal is acknowledged.
Therefore, the execution branches to the handler address.
set the STOP mode.
maskable interrupt request signal.
CHAPTER 15 STANDBY FUNCTION
User’s Manual U17716EJ2V0UD
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