UPD70F3713GC-8BS-A Renesas Electronics America, UPD70F3713GC-8BS-A Datasheet - Page 443

• Manufacturer Part Number: UPD70F3713GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3713GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(b) Timer trigger mode
Of the ANIn0 to ANIn3 pins, the analog input pin specified by the ADAnS.ADAnS1 and ADAnS.ADAnS0
bits is used for A/D conversion in this mode. The timer (motor control function) is used for the A/D
conversion start timing.
The timer trigger signal of A/D converter n is the timer interrupt request signal (TQTADT10, TQTADT11) of
the timer (motor control function). The TQTADT10 and TQTADT11 signals are connected to the TTRG01
and TTRG11 signals of A/D converter n (see Figure 11-2).
• Timer trigger of A/D converter 0: TQTADT10
• Timer trigger of A/D converter 1: TQTADT11
The TQTADT10 and TQTADT11 signals are set by using the TQ1AT00 to TQ1AT03 bits of TMQ1 option
register 2 (TQ1OPT2) and the TQ1AT10 to TQ1AT13 bits of TMQ1 option register 3 (TQ1OPT3). The
interrupt request signals of the motor control function that can be selected as a timer trigger signal are the
INTTP1CC0, INTTP1CC1, INTTQ1CC0, and INTTQ1OV signals (two or more signals can be selected).
When the ADAnM2.ADAnTMD1 bit is set to 1, A/D conversion is started at the rising edge of the timer
interrupt request signal (TQTADT10 or TQTADT11) set for the motor control function.
When the ADAnM0.ADAnCE bit is set to 1, the A/D converter waits for a trigger and, when the timer
interrupt request signal is input, starts A/D conversion.
After the end of A/D conversion, the conversion result is stored in A/Dn conversion result register m
(ADAnCRm) and, at the same time, an A/Dn conversion end interrupt request signal (INTADn) is
generated.
If the operation mode set by the ADAnM0.ADAnMD1 and ADAnM0.ADAnMD0 bits is the continuous select
mode or continuous scan mode, the conversion operation is repeated, with the next timer interrupt request
signal as the trigger, unless the ADAnM0.ADAnCE bit is cleared to 0. In the one-shot select mode or one-
shot scan mode, the A/D converter waits for a trigger.
When conversion is started, the ADAnM0.ADAnEF bit is set to 1 (conversion in progress). While the
converter waits for a trigger, however, the ADAnM0.ADAnEF bit = 0 (conversion stopped).
If the valid trigger is input during A/D conversion, the conversion is stopped and is executed again from the
beginning.
conversion is stopped and the converter waits for a trigger again.
Caution In timer trigger mode, make sure that the timer interrupt request signal (A/D conversions
Remark
start timing) is not generated at an interval shorter than the minimum number of
conversion
ADAnM1.ADAnFR0 bits. If the interrupt request signal is generated at an interval shorter
than the minimum number of conversion clocks, the last trigger is valid.
n = 0, 1
m = 0 to 3
If the ADAnM0, ADAnM2, and ADAnS registers are written during A/D conversion, the
clocks
CHAPTER 11 A/D CONVERTERS 0 AND 1
User’s Manual U17716EJ2V0UD
that
can
be
specified
by
the
ADAnM1.ADAnFR1
441
and