UPD70F3713GC-8BS-A Renesas Electronics America, UPD70F3713GC-8BS-A Datasheet - Page 432

• Manufacturer Part Number: UPD70F3713GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3713GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

430
(5) Successive approximation register (SAR)
(6) A/Dn conversion result registers 0 to 3 (ADAnCR0 to ADAnCR3), A/Dn conversion result registers 0H
(7) A/D converter n mode register 0 (ADAnM0) (n = 0, 1)
(8) A/D converter n mode register 1 (ADAnM1) (n = 0, 1)
(9) A/D converter n channel specification register (ADAnS) (n = 0, 1)
(10) A/D converter n mode register 2 (ADA2M2) (n = 0, 1)
(11) ANIn0 to ANIn3 pins (n = 0, 1)
(12) AV
The SAR is a 10-bit register that sets voltage tap data whose values from the array match the voltage values of
the analog input pins, 1 bit at a time starting from the most significant bit (MSB).
If data is set in the SAR all the way to the least significant bit (LSB) (end of A/D conversion), the contents of
the SAR (conversion results) are held in A/Dn conversion result registers 0 to 3 (ADAnCR0 to ADAnCR3) (n =
0, 1). When all the specified A/D conversion operations have ended, an A/Dn conversion end interrupt request
signal (INTADn) is generated.
to 3H (ADAnCR0H to ADAnCR3H) (n = 0, 1)
The ADAnCR0 to ADAnCR3 and ADAnCR0H to ADAnCR3H registers are registers that hold the A/D
conversion results. Each time A/D conversion ends, the conversion result is loaded from the successive
approximation register (SAR) and stored in the higher 10 bits of the ADAnCR0 to ADAnCR3 registers. The
lower 6 bits of these registers are always 0 when read.
The higher 8 bits of the result of A/D conversion are read from the ADAnCR0H to ADAnCR3H registers. To
read the result of A/D conversion in 16-bit units, specify the ADAnCR0 to ADAnCR3 registers. To read the
higher 8 bits, specify the ADAnCR0H to ADAnCR3H registers.
This register is used to specify the operation mode and controls the conversion operation.
This register is used to set the number of conversion clocks of the analog input to be A/D converted.
This register is used to specify the analog input pin to be A/D converted.
This register is used to specify the buffer mode and specify the mode in the hardware trigger mode.
The ANIn0 to ANIn3 pins are analog input pins for A/D converters 0 and 1. They input the analog signals to be
A/D converted.
Caution Make sure that the voltages input to ANIn0 to ANIn3 do not exceed the rated values. If a
This is the pin for inputting the reference voltage of A/D converters 0 and 1. It converts signals input to the
ANIn0 to ANIn3 pins to digital signals based on the voltage applied between AV
Always make the potential at the AV
1 are not used.
The operating voltage range of the AV
REF0
and AV
voltage higher than or equal to AV
of the absolute maximum ratings) is input to a channel, the conversion value of the channel
is undefined, and the conversion values of the other channels may also be affected.
REF1
pins
CHAPTER 11 A/D CONVERTERS 0 AND 1
REFn
REFn
User’s Manual U17716EJ2V0UD
pin the same as that at the EV
pin is V
REFn
DD
or lower than or equal to AV
= EV
DD
= AV
DDn
= AV
DD
pin even when A/D converters 0 and
REFn
= 4.5 to 5.5 V.
SSn
REFn
(even within the range
and AV
SSn
(n= 0, 1).