UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 1084

• Manufacturer Part Number: UPD70F3763GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-U 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3763GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-U, V850ES/JH3-U
21.2.2 USB host controller memory map
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
exist). The OHCI host controller, which is the main function of the USB host controller, is connected via the SRAM
interface of the CS1 space and the internal PCI bus bridge. The CPU and internal PCI bus bridge share the same
memory, and the CPU memory space and PCI memory space are linked. This relationship is defined by the PCI host
bridge registers and the OHCI host configuration registers that are accessed via the PCI host bridge registers.
The USB host controller is allocated in the CS1 space internally in the microcontroller (external pin CS1 does not
00280000H to 00281FFFH
002E0000H to 002E0FFFH
002E1000H to 002E10FFH
Address
0 0 2 F F F F F H
0 0 2 E 1 0 F F H
0 0 2 E 1 0 0 0 H
0 0 2 E 0 F F F H
0 0 2 E 0 0 0 0 H
0 0 2 D F F F F H
0 0 2 8 2 0 0 0 H
0 0 2 8 1 F F F H
0 0 2 8 0 0 0 0 H
0 0 2 7 F F F F H
0 0 2 5 0 0 0 0 H
0 0 2 4 F F F F H
0 0 2 0 0 0 0 0 H
Figure 21-2. USB Host Controller Memory Map
Table 21-1. Division of CPU Memory Space
PCI bridge register (256 bytes)
SRAM area (8 KB)
USB function area
Use prohibited
Use prohibited
Use prohibited
OHCI (4 KB)
8 or 16 bits
32 bits
Access
CHAPTER 21 USB HOST CONTROLLER (USBH)
SRAM area
OHCI area
PCI bus bridge register area
32-bit access
8- or 16-bit access
Area
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