UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 388

• Manufacturer Part Number: UPD70F3763GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-U 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3763GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(2) Operation timing in one-shot pulse output mode
(TIAB00 pin input)
External trigger input
INTTABnCC0 signal
(only when software
INTTABnCCk signal
TABnCCR0 register
TABnCCRk register
TOABn0 pin output
TOABnk pin output
(a) Notes on rewriting TABnCCRm register
trigger is used)
16-bit counter
To change the set value of the TABnCCRm register to a smaller value, stop counting once, and then change
the set value.
If the value of the TABnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
Note TAB1: TRGAB1 pin
When the TABnCCR0 register is rewritten from D
D
greater than D
than D
compared with the count value. The counter counts up to FFFFH and then counts up again from 0000H.
When the count value matches D
pin. When the count value matches D
TOABnk pin, and stops counting.
Therefore, the counter may output a pulse with a delay period or active period different from that of the one-
shot pulse that is originally expected.
Remark
TABnCE bit
00
> D
FFFFH
0000H
01
01
Note
and less than D
and D
k = 1 to 3,
n = 0, 1
k1
k0
and less than D
> D
k1
Delay
(D
, if the TABnCCRk register is rewritten when the count value of the 16-bit counter is
k0
)
Active level width
00
D
(D
, each set value is reflected as soon as the register has been rewritten and
k0
00
D
− D
k0
k0
k1
D
k0
and if the TABnCCR0 register is rewritten when the count value is greater
, the counter generates the INTTABnCCk signal and asserts the TOABnk
D
00
+ 1)
00
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
01
, the counter generates the INTTABnCC0 signal, deasserts the
(10000H + D
D
00
k0
Delay
to D
01
D
and the TABnCCRk register from D
k1
00
)
Active level width
D
(D
k1
01
− D
D
k1
k1
D
+ 1)
01
D
01
Delay
(D
k1
Active level width
D
)
(D
k1
01
− D
Page 388 of 1408
k0
k1
D
to D
+ 1)
01
k1
where