UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 1168

• Manufacturer Part Number: UPD70F3763GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-U 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3763GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(8) Registers/bits that must not be rewritten during DMA operation
(9)
(10) DMA start factor
(11) Read values of DSAn and DDAn registers
Set the following registers at the following timing when a DMA operation is not under execution.
[Registers]
[Settable timing]
• Bits 14 to 10 of DSAnH register
• Bits 14 to 10 of DDAnH register
• Bits 15, 13 to 8, and 3 to 0 of DADCn register
• Bits 6 to 3 of DCHCn register
Do not start two or more DMA channels with the same start factor. If two or more channels are started with the
same factor, DMA for which a channel has already been set may be started or a DMA channel with a lower priority
may be acknowledged earlier than a DMA channel with a higher priority. The operation cannot be guaranteed.
Values in the middle of updating may be read from the DSAn and DDAn registers during DMA transfer (n = 0 to 3).
For example, if the DSAnH register and then the DSAnL register are read when the DMA transfer source address
(DSAn register) is 0000FFFFH and the count direction is incremental (DADCn.SAD1 and DADCn.SAD0 bits = 00),
the value of the DSAn register differs as follows, depending on whether DMA transfer is executed immediately
after the DSAnH register is read.
(a) If DMA transfer does not occur while DSAn register is read
(b) If DMA transfer occurs while DSAn register is read
Be sure to set the following register bits to 0.
• The CPU can access the internal ROM and internal RAM when DMA transfer is being executed between the
• The CPU can access the internal ROM, and internal peripheral I/O when DMA transfer is being executed
• DSAnH, DSAnL, DDAnH, DDAnL, DBCn, and DADCn registers
• DTFRn.IFCn5 to DTFRn.IFCn0 bits
• Period from after reset to start of the first DMA transfer
• Time after channel initialization to start of DMA transfer
• Period from after completion of DMA transfer (TCn bit = 1) to start of the next DMA transfer
external memory and on-chip peripheral I/O.
between external memories.
<1> Read value of DSAnH register: DSAnH = 0000H
<2> Read value of DSAnL register: DSAnL = FFFFH
<1> Read value of DSAnH register: DSAnH = 0000H
<2> Occurrence of DMA transfer
<3> Incrementing DSAn register: DSAn = 00100000H
<4> Read value of DSAnL register: DSAnL = 0000H
CHAPTER 22 DMA FUNCTION (DMA CONTROLLER)
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