UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 70

• Manufacturer Part Number: UPD70F3763GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-U 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3763GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(b) Internal RAM (48 KB)
(c) Data-only RAM (8 KB)
48 KB are allocated to addresses 03FF3000H to 03FFEFFFH in the following products.
Accessing addresses 03FF0000H to 03FF2FFFH is prohibited.
•
A data-only RAM of 8 KB is allocated to addresses 00280000H to 00281FFFH in the V850ES/JG3-U and
V850ES/JH3-U.
The data-only RAM is used as a USB host area when the USB host controller is used. If the USB host
controller is not used, it can be used as a data-only RAM.
μ
Caution When using the data-only RAM area, the following two register settings are needed.
PD70F3764, 70F3769
• Select the clock that can be supplied to the data-only RAM by using the USB clock
• Enable the data-only RAM operation by using the USB function select register
select register (UCKSEL) (refer to 20.6.1(1)).
(UHCKMSK) (UHCKMSK.UHMSK bit = 0) (refer to 20.6.1(3)).
Physical address space
0 3 F F E F F F H
0 3 F F 3 0 0 0 H
0 3 F F 2 F F F H
0 3 F F 0 0 0 0 H
Figure 3-8. Data-Only RAM Area (8 KB)
Figure 3-7. Internal RAM Area (48 KB)
Access-prohibited
Access-prohibited
(Data-only RAM
USB host area
8 KB)
area
area
Access-prohibited
Internal RAM
(48 KB)
area
Logical address space
0 0 2 8 2 0 0 0 H
0 0 2 8 1 F F F H
0 0 2 8 0 0 0 0 H
0 0 2 7 F F F F H
Logical address space
F F F F 3 0 0 0 H
F F F F 2 F F F H
F F F F 0 0 0 0 H
F F F F E F F F H
CHAPTER 3 CPU FUNCTION
Page 70 of 1408