UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 404

• Manufacturer Part Number: UPD70F3763GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-U 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3763GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
TABnCTL1
TABnCTL0
TABnIOC0
(a) TABn control register 0 (TABnCTL0)
(b) TABn control register 1 (TABnCTL1)
(c) TABn I/O control register 0 (TABnIOC0)
Note The setting is invalid when the TABnCTL1.TABnEEE bit = 1
Remark
TABnOL3
TABnSYE
TABnCE
0/1
0/1
0
n = 0, 1
TABnOE3 TABnOL2 TABnOE2
TABnEST
0/1
Figure 8-31. Register Setting in Free-Running Timer Mode (1/3)
0
0
Figure 8-31. Register Setting in Free-Running Timer Mode (2/3)
TABnEEE
0/1
0/1
0
0/1
0
0
TABnOL1
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
0/1
0
0
TABnMD2 TABnMD1 TABnMD0
TABnCKS2 TABnCKS1 TABnCKS0
TABnOE1 TABnOL0 TABnOE0
0/1
0/1
1
0/1
0/1
0
0/1
0/1
1
1, 0, 1:
Free-running mode
0: Disable TOABn0 pin output
1: Enable TOABn0 pin output
Setting of output level with
operation of TOABn0 pin disabled
0: Low level
1: High level
0: Disable TOABn1 pin output
1: Enable TOABn1 pin output
Setting of output level with
operation of TOABn1 pin
disabled
0: Low level
1: High level
0: Disable TOABn2 pin output
1: Enable TOABn2 pin output
Setting of output level with
operation of TOABn2 pin
disabled
0: Low level
1: High level
0: Disable TOABn3 pin output
1: Enable TOABn3 pin output
Setting of output level with
operation of TOABn3 pin
disabled
0: Low level
1: High level
Select count clock
0: Stop counting
1: Enable counting
0: Operate with count
1: Count by external
clock selected by
TABnCKS0 to TABnCKS2 bits
event count input signal
Page 404 of 1408
Note