UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 1229
UPD70F3763GC-UEU-AX
Manufacturer Part Number
UPD70F3763GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-U 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3763GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
75
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3763GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-U, V850ES/JH3-U
25.5 IDLE2 Mode
25.5.1 Setting and operation status
normal operation mode.
on-chip peripheral functions stops.
The CPU, PLL, and other on-chip peripheral functions stop operating. However, the on-chip peripheral functions that can
operate with the subclock or an external clock continue operating.
on-chip peripheral functions, PLL, and flash memory. However, because the PLL and flash memory are stopped, a setup
time for the PLL and flash memory is required when IDLE2 mode is released.
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
The IDLE2 mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 10 and setting the PSC.STP bit to 1 in the
In the IDLE2 mode, the clock oscillator continues operation but clock supply to the CPU, PLL, flash memory, and other
As a result, program execution stops and the contents of the internal RAM before the IDLE2 mode was set are retained.
Table 25-7 shows the operating status in the IDLE2 mode.
The IDLE2 mode can reduce the power consumption more than the IDLE1 mode because it stops the operations of the
Cautions 1. Insert five or more NOP instructions after the instruction that stores data in the PSC register to
2. If the IDLE2 mode is set while an unmasked interrupt request signal is being held pending, the
set the IDLE2 mode.
IDLE2 mode is released immediately by the pending interrupt request.
CHAPTER 25 STANDBY FUNCTION
Page 1229 of 1408
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