UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 15

• Manufacturer Part Number: UPD70F3763GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-U 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3763GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) ................................................................. 1232
CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION............................................. 1256
CHAPTER 24 KEY INTERRUPT FUNCTION ................................................................................... 1304
21.7 OHCI Host Controller ........................................................................................................... 1255
22.1 Features ................................................................................................................................ 1232
22.2 Configuration........................................................................................................................ 1233
22.3 Registers ............................................................................................................................... 1234
22.4 Transfer Targets................................................................................................................... 1243
22.5 Transfer Modes .................................................................................................................... 1243
22.6 Transfer Types ..................................................................................................................... 1244
22.7 DMA Channel Priorities ....................................................................................................... 1245
22.8 Time Related to DMA Transfer............................................................................................ 1245
22.9 DMA Transfer Start Factors ................................................................................................ 1246
22.10 DMA Abort Factors .............................................................................................................. 1247
22.11 End of DMA Transfer ........................................................................................................... 1247
22.12 Operation Timing.................................................................................................................. 1247
22.13 Cautions ................................................................................................................................ 1252
23.1 Features ................................................................................................................................ 1256
23.2 Non-Maskable Interrupts ..................................................................................................... 1267
23.3 Maskable Interrupts ............................................................................................................. 1272
23.4 Software Exception.............................................................................................................. 1287
23.5 Exception Trap ..................................................................................................................... 1290
23.6 External Interrupt Request Input Pins (NMI and INTP00 to INTP18)............................... 1294
23.7 Interrupt Acknowledge Time of CPU.................................................................................. 1302
23.8 Periods in Which Interrupts Are Not Acknowledged by CPU ......................................... 1303
23.9 Cautions ................................................................................................................................ 1303
24.1 Function ................................................................................................................................ 1304
21.6.2 PCI host bridge registers.............................................................................................................1242
21.7.1 OHCI host controller functions ....................................................................................................1255
21.7.2 OHCI host configuration registers ...............................................................................................1256
21.7.3 OHCI operational registers..........................................................................................................1269
21.7.4 Interruption from USB host controller..........................................................................................1298
23.2.1 Operation ....................................................................................................................................1269
23.2.2 Restore .......................................................................................................................................1270
23.2.3 NP flag ........................................................................................................................................1271
23.3.1 Operation ....................................................................................................................................1272
23.3.2 Restore .......................................................................................................................................1274
23.3.3 Priorities of maskable interrupts..................................................................................................1275
23.3.4 Interrupt control register (xxICn) .................................................................................................1279
23.3.5 Interrupt mask registers 0 to 5 (IMR0 to IMR5) ...........................................................................1283
23.3.6 In-service priority register (ISPR) ................................................................................................1285
23.3.7 ID flag .........................................................................................................................................1286
23.3.8 Watchdog timer mode register 2 (WDTM2).................................................................................1286
23.4.1 Operation ....................................................................................................................................1287
23.4.2 Restore .......................................................................................................................................1288
23.4.3 EP flag ........................................................................................................................................1289
23.5.1 Illegal opcode..............................................................................................................................1290
23.5.2 Debug trap ..................................................................................................................................1292
23.6.1 Noise elimination.........................................................................................................................1294
23.6.2 Edge detection ............................................................................................................................1294