UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 883
UPD70F3763GC-UEU-AX
Manufacturer Part Number
UPD70F3763GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-U 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3763GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
75
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
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Company:
Part Number:
UPD70F3763GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-U, V850ES/JH3-U
19.16.3 Slave operation
requiring a significant change of the operation status, such as stop condition detection during communication) is
necessary.
the INTIICn interrupt servicing performs only status change processing and that the actual data communication is
performed during the main processing.
these flags to the main processing instead of the INTIICn signal.
using the communication mode flag and ready flag (the processing of the stop condition and start condition is performed
by interrupts, conditions are confirmed by flags).
device stops returning ACK, transfer is complete.
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
The following shows the processing procedure of slave operation.
Basically, the operation of the slave device is event-driven. Therefore, processing by an INTIICn interrupt (processing
The following description assumes that data communication does not support extension codes. Also, it is assumed that
Therefore, the following three flags are prepared so that the data transfer processing can be performed by passing
(1) Communication mode flag
(2) Ready flag
(3) Communication direction flag
The following shows the operation of the main processing block during slave operation.
I
For transmission, the transmission operation is repeated until the master device stops returning ACK. When the master
2
This flag indicates the following communication statuses.
Clear mode:
Communication mode: Data communication in progress (valid address detection stop condition detection, ACK from
This flag indicates that data communication is enabled. This is the same status as an INTIICn interrupt during normal
data transfer. This flag is set in the interrupt processing block and cleared in the main processing block. The ready
flag for the first data for transmission is not set in the interrupt processing block, so the first data is transmitted without
clear processing (the address match is regarded as a request for the next data).
This flag indicates the direction of communication and is the same as the value of IICSn.TRCn bit.
C0n starts and waits for the communication enable status. When communication is enabled, I
I
2
C
Data communication not in progress
master not detected, address mismatch)
Figure 19-20. Overview of Software During Slave Operation
INTIICn signal
Setting, etc.
Interrupt servicing
Setting, etc.
Data
Flag
Main processing
CHAPTER 19 I
2
C0n performs transfer
Page 883 of 1408
2
C BUS
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