UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 336

• Manufacturer Part Number: UPD70F3763GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-U 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3763GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(4) TABn I/O control register 1 (TABnIOC1)
The TABnIOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIABn0
to TIABn3 pins).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
TABnIOC1
(n = 0, 1)
After reset: 00H
Cautions 1. Rewrite
TABnIS7
TABnIS5
TABnIS3
TABnIS1
TABnIS7
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
7
TABnIS6
TABnIS4
TABnIS2
TABnIS0
TABnIS6 TABnIS5 TABnIS4 TABnIS3 TABnIS2 TABnIS1 TABnIS0
R/W
2. The TABnIS7 to TABnIS0 bits are valid only in the free-
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
6
TABnCTL0.TABnCE bit = 0.
written when the TABnCE bit = 1.)
mistakenly performed, clear the TABnCE bit to 0 and then
set the bits again.
running timer mode and the pulse width measurement
mode.
possible.
Address:
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
Capture trigger input signal (TIABn2 pin) valid edge detection
Capture trigger input signal (TIABn3 pin) valid edge setting
Capture trigger input signal (TIABn1 pin) valid edge setting
Capture trigger input signal (TIABn0 pin) valid edge setting
5
In all other modes, a capture operation is not
the
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
TAB0IOC1 FFFFF543H, TAB1IOC1 FFFFF563H
TABnIS7
4
3
to
TABnIS0
(The same value can be
2
If rewriting was
bits
1
when
0
the
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