M30260F6AGP#D5 Renesas Electronics America, M30260F6AGP#D5 Datasheet - Page 142

• Manufacturer Part Number: M30260F6AGP#D5
• Description: IC M16C MCU FLASH 48K 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#D5

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

R
R
M
e
E
1
. v
J
6
Figure 12.3.6. TB2SC Registers
0
C
2
9
0 .
B
2 /
0
0
6
2
Timer B2 Special Mode Register
A
0
b7
F
NOTES:
2
e
G
0 -
0
b6
b
1. Write to this register after setting the PRC1 bit in the PRCR register to 1 (write enabled).
2. If the INV11 bit is 0 (three-phase mode 0) or the INV06 bit is 1 (triangular wave modulation mode), set this bit to 0 (timer
3. When setting the IVPCR1 bit to 1 (three-phase output forcible cutoff by SD pin input enabled), Set the PD8
4. Related pins are U(P8
5. When this bit is used in delayed trigger mode 0, set bits TB0EN and TB1EN to 1 (A/D trigger mode).
6. When setting the TB2SEL bit to 1 (underflow of TB2 interrupt generation frequency setting counter[ICTB2]), set the INV02
NOTES:
2.Case of INV03 = 0(Three-phase motor control timer output disabled)
NOTE:
The effect of SD pin input is below.
1.Case of INV03 = 1(Three-phase motor control timer output enabled)
forcrible cutoff disable)
forcrible cutoff disable)
forcrible cutoff enable)
o r
forcrible cutoff enable)
1 .
2
(Three-phase output
(Three-phase output
(Three-phase output
(Three-phase output
B2 underflow).
mode).
and set the IVPCR1 bit to 0 after forcible cutoff, pins U, U, V, V, W, and W are exit from the high-impedance state. If a low-
level (“L”) signal is applied to the SD pin, three-phase motor control timer output will be disabled (INV03=0). At this time,
when the IVPCR1 bit is 0, pins U, U, V, V, W, and W become programmable I/O ports. When the IVPCR1 bit is set to 1,
pins U, U, V, V, W, and W are placed in a high-impedance state regardless of which function of those pins is used.
bit to 1 (three-phase motor control timer function).
1. When "L" is applied to the SD pin, INV03 bit is changed to 0 at the same time.
2. The value of the port register and the port direction register becomes effective.
3. When SD function is not used, set to 0 (Input) in PD8
4. To leave the high-impedance state and restart the three-phase PWM signal output after the three-phase PWM signal
0
1. The three-phase output forcrible cutoff function becomes effective if the INPCR1 bit is set to 1 (three-phase output
0
b5
, 5
u
0
output forced cutoff, set the IVPCR1 bit to 0 after the SD pin input level becomes high (“H”).
p
forcrible cutoff function enable) even when the INV03 bit is 0 (three-phase motor control timer output disalbe)
IVPCR1 bit
IVPCR1 bit
2
b4
(
0
M
0
b3
1
0
1
0
7
1
6
b2
C
page 123
b1
2 /
6
b0
, A
0
Bit Symbol
), U(P8
M
PWCON
IVPCR1
TB2SEL
(b6-b5)
TB0EN
TB1EN
(b7)
1
Symbol
TB2SC
f o
6
SD pin inputs
SD pin inputs
C
3
1
), V(P7
2
2 /
9
6
Timer B0 operation mode
select bit
Timer B1 operation mode
select bit
Three-phase output port
SD control bit 1
H
H
Timer B2 reload timing
switch bit
Trigger select bit
L
L
H
H
L
L
Reserved bits
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
, B
(1)
(1)
(1)
2
), V(P7
M
Address
039E
(3)
1
Bit Name
6
3
C
(2)
16
), W(P7
(3, 4, 7)
2 /
6
Three-phase PWM output
Three-phase PWM output
) T
(6)
Peripheral input/output
Peripheral input/output
Peripheral input/output
4
Status of U/V/W pins
Status of U/V/W pins
), W(P7
5
or input/output port
or input/output port
or input/output port
Input/output port
High impedance
High impedance
and pullup to "H" in SD pin from outside.
0: Timer B2 underflow
1: Timer A output at odd-numbered
0: Three-phase output forcible cutoff by SD pin input
1: Three-phase output forcible cutoff by SD pin input
0: Other than A/D trigger mode
1: A/D trigger mode
0: TB2 interrupt
1: Underflow of TB2 interrupt
0: Other than A/D trigger mode
1: A/D trigger mode
5
After Reset
X0000000
Set to 0
). When a high-level ("H") signal is applied to the SD pin
(high impedance) disabled
(high impedance) enabled
generation frequency setting counter [ICTB2]
2
(4)
(2)
Function
Three-phase output
forcrible cutoff
Three-phase output
forcrible cutoff
(5)
(5)
Remarks
Remarks
(1)
5
bit to 0 (= input
RW
RW
RW
RW
RW
RW
RW
12. Timer