M30260F6AGP#D5 Renesas Electronics America, M30260F6AGP#D5 Datasheet - Page 62

• Manufacturer Part Number: M30260F6AGP#D5
• Description: IC M16C MCU FLASH 48K 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#D5

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

R
R
M
e
E
. v
J
1
Figure 7.6. PCLKR Register and PM2 Register
0
6
2
9
C
0 .
B
2 /
0
0
2
6
0
F
A
2
e
0 -
b
G
Peripheral Clock Select Register
1 .
0 0
2
b7
Processeor Mode Register 2
o r
NOTE:
0
, 5
NOTES:
0
b7
u
b6
1. Write to this register after setting the PRC0 bit in PRCR register to 1 (write enable).
2
p
1. Write to this register after setting the PRC1 bit in the PRCR register to 1 (write enable).
2. The PM20 bit becomes effective when PLC07 bit in the PLC0 register is set to 1 (PLL on). Change the PM20
3. Once this bit is set to 1, it cannot be cleared to 0 by program.
4. Writting to the following bits has no effect when the PM21 bit is set to 1:
5. Setting the PM22 bit to 1 results in the following conditions:
6. For NMI function, the PM24 bit must be set to 1(NMI function). Once this bit is set to 1, it cannot be set to 0 by
7. SD input is valid regardless of the PM24 setting.
0
b6
b5
(
0
M
bit when the PLC07 bit is set to 0 (PLL off). Set the PM20 bit to 0 (2 waits) when PLL clock > 16MHz.
program.
7
b5
Do not execute WAIT instruction when the PM21 bit is set to 1.
• The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer
• The CM10 bit in the CM1 register cannnot be written. (Writing 1 has no effect, stop mode is not entered.)
• The watchdog timer does not stop in wait mode.
•
b4
0 0 0
1
count source.
The on-chip oscillator continues oscillating even if the CM21 bit in the CM2 register is set to "0" (main clock or
PLL clock) (system clock of count source selected by the CM21 bit is valid)
6
CM02 bit in the CM0 register
CM05 bit in the CM0 register (main clock is not halted)
CM07 bit in the CM0 register (CPU clock source does not change)
CM10 bit in the CM1 register (stop mode is not entered)
CM11 bit in the CM1 register (CPU clock source does not change)
CM20 bit in the CM2 register (oscillation stop, re-oscillation detection function settings do not change)
All bits in the PLC0 register (PLL frequency synthesizer setting do not change)
b4
b3
C
page 43
2 /
b3
0
b2
6
b2
, A
b1
b1
M
b0
f o
b0
1
6
Bit Symbol
3
C
PCLK0
PCLK1
(b4-b2)
PCLK5
(b7-b6)
Bit Symbol
2
(b7-b5)
2 /
9
PM20
PM21
PM22
PM24
Symbol
PCLKR
(b3)
Symbol
PM2
6
, B
(1)
M
Timers A, B clock select bit
(Clock source for the timers A,
B, the timer S, the dead timer,
SI/O3, SI/O4 and multi-master
I
SI/O clock select bit
(Clock source for UART0 to
UART2)
Reserved bit
Clock output function
expansion select bit
Reserved bit
2
Specifying wait when
accessing SFR (2)
System clock protective
bit (3,4)
WDT count source
protective bit
Reserved bit
P8
Nothing is assigned. When write, set to 0.
When read, thecontent is undefined
(1)
C bus)
1
6
5
/NMI configuration bit(6,7)
C
2 /
6
Bit Name
Bit Name
) T
Address
025E
(3,5)
Address
001E
16
16
0: 2 waits
1: 1 wait
0: Clock is protected by PRCR
1: Clock modification disabled
0: CPU clock is used for the
1: On-chip oscillator clock is used
Set to 0
0: P
1: NMI function
After Reset
XXX00000
After Reset
00000011
0: f
1: f
0: f
1: f
Set to 0
Refer to Table 7.5.3.1
Set to 0
register
watchdog timer count source
for the watchdog timer count
source
8
2
1
2
1
5
SIO
SIO
function (NMI disabled)
2
2
Function
Function
7. Clock Generation Circuit
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW