M30260F6AGP#D5 Renesas Electronics America, M30260F6AGP#D5 Datasheet - Page 260

• Manufacturer Part Number: M30260F6AGP#D5
• Description: IC M16C MCU FLASH 48K 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#D5

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

R
R
M
e
E
1
. v
J
6
Figure 17.5.1. FMR0 and FMR1 register
0
C
2
9
0 .
B
2 /
0
0
6
2
A
0
F
2
e
G
0 -
b
o r
1 .
2
0
Flash memory control register 0
, 5
u
b7 b6 b5 b4 b3 b2 b1 b0
Flash memory control register 1
NOTES:
b7 b6 b5 b4 b3 b2 b1 b0
NOTES:
0
p
2
1. When setting this bit to “1”, set to “1” immdediately after setting it first to “0”. Do not generate an interrupt
2. Set this bit to “1” immediately after setting it first to “0” while the FMR01 bit is set to “1”. Do not generate
3. Set this bit in a pace other than the flash memory by program. When this bit is set to 1, access to flash
4. This bit is set to “0” by executing the clear status command.
5. This bit is enabled when the FMR01 bit is set to “1” (CPU rewrite mode). This bit can be set to “1” when
1. Set this bit to “1” immediately after setting it first to “0”. Do not generate an interrupt or a DMA transfer
2. Set this bit to “1” immediately after setting it first to “0”. Do not generate an interrupt or a DMA transfer
3. When rewriting more than 100 times, set this bit to “1” (with wait state). When the FMR17 bit is “1” (with
(
0
M
or a DMA transfer between setting the bit to “0” and setting it to “1”. Set this bit while the P8
is “H” when selecting the NMI function. Set by program in a space other than the flash memory in EW0
mode. Set this bit to read alley mode and “0”
an interrupt or a DMA transfer between setting this bit to “0” and setting it to “1”.
memory will be denied. To set this bit to 0 after setting it to 1, wait for 10 sec. or more after setting it to
1. To read data from flash memory after setting this bit to 0, maintain tps wait time before accessing
flash memory.
the FMR01 bit is set to “0”. However, the flash memory does not enter low-power consumption status
0
between setting the bit to “0” and setting it to “1”. Set this bit while the P8
NMI function is selected. If the FMR01 bit is set to “0”, the FMR01 bit and FMR11 bit are both set to “0”
after setting to “0”.
wait state), regardless of the content of the PM17 bit, 1 wait is inserted at the access to the block A and
B. Regardless of the content of the FMR17 bit, access to other block and the internal RAM is
determined be PM17 bit setting.
0
0
7
1
6
0
C
page 241
2 /
6
, A
M
1
f o
Bit symbol
Bit symbol
6
FMR00
FMR01
FMR02
FMSTP
(b5-b4)
FMR06
FMR07
C
FMR11
(b3-b2)
FMR16
FMR17
3
(b0)
(b4)
(b5)
2
2 /
9
Symbol
Symbol
6
FMR0
FMR1
, B
RY/BY status flag
CPU rewrite mode select bit
(1)
Block 0, 1 rewrite enable bit
(2)
Flash memory stop bit
(3, 5)
Program status flag
Erase status flag
EW1 mode select bit (1)
Reserved bit
Nothing is assigned. When write, set to “0”.
When read, its contect is indeterminate.
Reserved bit
Block 0 to 3 rewrite enable
bit (2)
Block A, B access wait bit
(3)
Reserved bit
Reserved bit
M
1
6
C
2 /
Bit name
Bit name
Address
Address
6
01B7
01B5
) T
16
16
(4)
(4)
After reset
00000001
000XXX0X
After reset
Set write protection for user ROM area
(see Table 17.5.2.1)
0: Busy (during writing or erasing)
1: Ready
0: Disables CPU rewrite mode
1: Enables CPU rewrite mode
Set to “0”
0: Terminated normally
1: Terminated in error
0: Terminated normally
1: Terminated in error
When read, its content is indeterminate
0: Starts flash memory operation
1: Stops flash memory operation
(Enters low-power consumption state
and flash memory reset)
0: EW0 mode
1: EW1 mode
When read, its content is indeterminate
Set to “0”
Set write protection for user ROM area
(see Table 17.5.2.1)
0: Disable
1: Enable
0: PM17 enabled
1: With wait state (1 wait)
(Disables software command)
(Enables software commands)
2
2
5
/NMI/SD pin is “H” when the
Function
Function
5
/NMI/SD pin
17. Flash Memory Version
RW
RW
RW
RW
RW
RO
RO
RW
RO
RO
RW
RO
RW
RW
RW