M30260F6AGP#D5 Renesas Electronics America, M30260F6AGP#D5 Datasheet - Page 251

• Manufacturer Part Number: M30260F6AGP#D5
• Description: IC M16C MCU FLASH 48K 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#D5

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M
R
R
17.2 Memory Map
e
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Figure 17.2.1. Flash Memory Block Diagram (ROM capacity 64K byte)
0
C
The flash memory contains the user ROM area and the boot ROM area (reserved area). Figures 17.2.1 to
17.2.3 show the flash memory block diagram. The user ROM area has space to store the microcomputer
operation program in single-chip mode and a separate 2-Kbyte space as the block A and B.
The user ROM area is divided into several blocks. The user ROM area can be rewritten in CPU rewrite,
standard serial input/output, and parallel input/output modes. However, if block 0 and 1 are rewritten in
CPU rewrite mode, setting the FMR02 bit in the FMR0 register to “1” (block 0, 1 rewrite enabled) and the
FMR16 bit in the FMR1 register to “1”(blocks 0 to 3 rewrite enabled) enable rewriting. Also, if blocks 2 to 3
are rewritten in CPU rewrite mode, setting the FMR16 bit in the FMR1 register to “1” (blocks 0 to 3 rewrite
enabled) enables writing. Setting the PM10 bit in the PM1 register to “1”(data area access enabled) for
block A and B enables to use.
2
9
0 .
2 /
B
0
0
6
2
A
0 F 0 0 0 0
0 F 7 F F F
0 F 8 0 0 0
0 F B F F F
0 F C 0 0 0
0 F D F F F
0 F E 0 0 0
0 F F F F F
0 0 F 0 0 0
0 0 F 7 F F
0 0 F 8 0 0
0 0 F F F F
0
F
2
e
G
0 -
b
o r
1 .
2
1 6
1 6
1 6
1 6
1 6
0
u
1 6
1 6
1 6
1 6
1 6
1 6
, 5
1 6
0
p
2
(
0
M
B l o c k 3 : 3 2 K b y t e s (5)
B l o c k 2 : 1 6 K b y t e s (5)
0
B l o c k 1 : 8 K b y t e s (3)
B l o c k 0 : 8 K b y t e s (3)
B l o c k B : 2 K b y t e s (2)
B l o c k A : 2 K b y t e s (2)
1
7
6
B l o c k 2 : 1 6 K b y t e s
U s e r R O M a r e a
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2 /
6
, A
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f o
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3
2
2 /
9
6
, B
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NOTES:
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1. To specify a block, use the maximum even address in the block.
2. Blocks A and B are enabled to use when the PM10 bit in the PM1
3. Blocks 0 and 1 are enabled for programs and erases when the
4. The boot ROM area is reserved. Do not access.
5. Blocks 2 and 3 are enabled for programs and erases when the
register is set to "1".
FMR02 bit in the FMR0 register is set to "1" and the FMR16 bit in
the FMR1 register is set to "1". (CPU rewrite mode only)
FMR16 bit in the FMR1 register is set to "1". (CPU rewrite mode
only)
0 F F F F F
0 F F 0 0 0
1 6
1 6
B o o t R O M a r e a
4 K b y t e s (4)
17. Flash Memory Version