M30260F6AGP#D5 Renesas Electronics America, M30260F6AGP#D5 Datasheet - Page 90

• Manufacturer Part Number: M30260F6AGP#D5
• Description: IC M16C MCU FLASH 48K 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#D5

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

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6
Table 9.4.2.1. IPL Level That is Set to IPL When A Software or Special Interrupt Is Accepted
0
Figure 9.4.1.1. Interrupt response time
2
C
9
9.4.1 Interrupt Response Time
9.4.2 Variation of IPL when Interrupt Request is Accepted
0 .
B
2 /
Figure 9.4.1.1 shows the interrupt response time. The interrupt response or interrupt acknowledge time
denotes the time from when an interrupt request is generated till when the first instruction in the interrupt
routine is executed. Specifically, it consists of the time from when an interrupt request is generated till
when the instruction then executing is completed ((a) in Figure 9.4.1.1) and the time during which the
interrupt sequence is executed ((b) in Figure 9.4.1.1).
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set
in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed
in Table 9.4.2.1 is set in the IPL. Shown in Table 9.4.2.1 are the IPL values of software and special
interrupts when they are accepted.
Watchdog timer, NMI, Oscillation stop and re-oscillation detection,
voltage down detection
Software, address match, DBC, single-step
0
0
6
2
A
0
F
2
e
G
0 -
b
1 .
o r
2
0
, 5
u
0
p
Interrupt request generated
2
(a) The time from when an interrupt request is generated till when the instruction then
(b) The time during which the interrupt sequence is executed. For details, see the table
0
(
M
0
Interrupt sources
executing is completed. The length of this time varies with the instruction being
executed. The DIVX instruction requires the longest time, which is equal to 30 cycles
(without wait state, the divisor being a register).
below. Note, however, that the values in this table must be increased 2 cycles for the
DBC interrupt and 1 cycle for the address match and single-step interrupts.
7
1
6
C
_______
Interrupt vector address
page 71
2 /
6
, A
Instruction
M
Even
Even
Odd
Odd
_________
1
f o
(a)
6
C
3
Interrupt response time
2
2 /
9
Interrupt request acknowledged
6
, B
M
Interrupt sequence
1
6
SP value
C
Even
Even
Odd
Odd
2 /
6
(b)
) T
Without wait
18 cycles
19 cycles
19 cycles
20 cycles
interrupt routine
Instruction in
Level that is set to IPL
Time
Not changed
7
9. Interrupt