M30260F6AGP#D5 Renesas Electronics America, M30260F6AGP#D5 Datasheet - Page 331

• Manufacturer Part Number: M30260F6AGP#D5
• Description: IC M16C MCU FLASH 48K 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#D5

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

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19.7.3 Three-phase Motor Control Timer Function
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When the IVPCR1 bit in the TB2SC register is set to 1 (three-phase output forced cutoff by SD pin input
(high-impedance) enabled), the INV03 bit in the INVC0 register is set to 1 (three-phase motor control
timer output enabled), and a low-level ("L") signal is applied to the SD pin while a three-phase PWM
signal is output, the MCU is forced to cutoff and pins U, U, V, V, W, and W are placed in a high-impedance
state and the INV03 bit is set to 0 (three-phase motor control timer output disabled).
To resume the three-phase PWM signal output from pins U, U, V, V, W, and W, set the INV03 bit to 1 and
the IVPCR1 bit to 0 (three-phase output forced cutoff disabled) after the SD pin level becomes "H". Then
set the IVPCR1 bit to 1 (three-phase output forced cutoff enabled) in order to enable the three-phase
output forced cutoff function by input to the SD pin again.
The INV03 bit cannot be set to 1 while an "L" signal is input to the SD pin. To set the INV03 bit to 1 after
forcible cutoff, write 1 to the INV03 bit and read the bit to ensure that it is set to 1 by program. Then set the
IVPCR1 bit to 1 after setting it to 0.
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19.7.2.3 Timer B (Pulse Period/pulse Width Measurement Mode)
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1. The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR (i = 0 to 2)
2. The IR bit in the TBiIC register (i=0 to 2) goes to “1” (interrupt request), when an effective edge of
3. If the source of interrupt cannot be identified by the MR3 bit such as when the measurement pulse
4. To set the MR3 bit to “0” (no overflow), set TBiMR register with setting the TBiS bit to “1” and
5. Use the IR bit in the TBiIC register to detect only overflows. Use the MR3 bit only to determine the
6. When the count is started and the first effective edge is input, an indeterminate value is transferred
7. The value of the counter is indeterminate at the beginning of a count. MR3 may be set to “1” and
8. For pulse width measurement, pulse widths are successively measured. Use program to check
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register before setting the TBiS bit in the TABSR register to “1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)
regardless whether after reset or not. To clear the MR3 bit to “0” by writing to the TBiMR register
while the TBiS bit is set to “1” (count starts), be sure to set the TM0D0, TM0D1, MR0, MR1, TCK0
and TCK1 bits to the same value as previously written and the MR2 bit to "0".
a measurement pulse is input or timer Bi is overflowed. The factor of interrupt request can be
determined by use of the MR3 bit in the TBiMR register within the interrupt routine.
input and a timer overflow occur at the same time, use another timer to count the number of times
timer B has overflowed.
counting the next count source after setting the MR3 bit to “1” (overflow).
interrupt factor within the interrupt routine.
to the reload register. At this time, timer Bi interrupt request is not generated.
timer Bi interrupt request may be generated between the count start and an effective edge input.
whether the measurement result is an “H” level width or an “L” level width.
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19. Usage Notes