M30260F6AGP#D5 Renesas Electronics America, M30260F6AGP#D5 Datasheet - Page 169

• Manufacturer Part Number: M30260F6AGP#D5
• Description: IC M16C MCU FLASH 48K 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#D5

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

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R
M
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Table 13.1.2.1. UART Mode Specifications
6
0
NOTES:
Transfer data format
Transfer clock
Transmission, reception control
Transmission start condition
Reception start condition
data from
Error detection
Select function
13.1.2. Clock Asynchronous Serial I/O (UART) Mode
Interrupt request
generation timing
2
9
C
0 .
B
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 13.1.2.1 lists the specifications of the UART mode.
1. If an overrun error occurs, bits 8 to 0 in UiRB register are undefined. The IR bit in the SiRIC register remains
2. The U0IRS and U1IRS bits respectively are the bits "0" and "1" in the UCON register; the U2IRS bit is the bit 4 in
2 /
0
0
2
6
unchanged.
the U2C1 register.
0
A
F
2
e
0 -
G
b
1 .
2
o r
Item
0
, 5
u
0
p
2
0
(
M
0
7
1
6
C
page 150
2 /
6
, A
M
• Character bit (transfer data): Selectable from 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable from odd, even, or none
• Stop bit: Selectable from 1 or 2 bits
• The CKDIR bit in the UiMR(i=0 to 2) register is set to "0" (internal clock) : fj/(16(n+1))
• CKDIR bit is set to “1” (external clock ) : f
• Selectable from CTS function, RTS function or CTS/RTS function disable
• Before transmission can start, the following requirements must be met
_
_
_
• Before reception can start, the following requirements must be met
_
_
• For transmission, one of the following conditions can be selected
_
_
• For reception
• Overrun error
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the bit one before the last stop bit of the next data
• Framing error
• Parity error
• Error sum flag
• LSB first, MSB first selection
• Serial data logic switch (UART2)
• T
• Separate CTS/RTS pins (UART0)
• UART1 pin remapping selection
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
CTS
The UART1 pin can be selected from the P6
_________
fj = f
f
UiTB register to the UARTi transmit register (at start of transmission)
This error occurs when the number of stop bits set is not detected
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
This function reverses the logic of the transmit/receive data. The start and stop bits
are not reversed.
This function reverses the polarities of hte T
logic levels of all I/O data is reversed.
f o
1
The TE bit in the UiC1 register is set to "1" (transmission enabled)
The TI bit in the UiC1 register "0" (data present in UiTB register)
If CTS function is selected, input “L” to the CTSi pin
The RE bit in the UiC1 register is set to "1" (reception enabled)
Start bit detection
The UiIRS bit
The UiIRS bit is set to "1" (transfer completed): when the serial I/O finished sending
EXT
X
6
_______
the UARTi transmit register
D, R
3
C
2
: Input from CLKi pin.
1SIO
0
2 /
9
and RTS
6
X
, B
D I/O polarity switch (UART2)
, f
_______ _______
2SIO
_________
M
1
(2)
(1)
, f
6
0
C
8SIO
_______
are input/output from separate pins
is set to "0" (transmit buffer empty): when transferring data from the
2 /
6
, f
) T
32SIO
. n: Setting value of UiBRG register
n :Setting value of UiBRG register
Specification
_______
EXT
_______
X
7
/(16(n+1))
D pin output and R
to P6
_______ _______
4
or P7
3
to P7
X
0
D pin input. The
00
.
00
16
16
to FF
to FF
13. Serial I/O
16
16