M30260F6AGP#D5 Renesas Electronics America, M30260F6AGP#D5 Datasheet - Page 335

• Manufacturer Part Number: M30260F6AGP#D5
• Description: IC M16C MCU FLASH 48K 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#D5

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

R
R
M
e
E
1
. v
J
6
0
C
2
9
0 .
B
2 /
8. If the CPU reads the A/D register i (i = 0 to 7) at the same time the conversion result is stored in the A/
9. If A/D conversion is forcibly terminated while in progress by setting the ADST bit in the ADCON0
10.When setting the ADST bit in the ADCON register to "0" to terminate a conversion forcefully by the
0
0
6
D register i after completion of A/D conversion, an incorrect value may be stored in the A/D register i.
This problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for
CPU clock.
register to “0” (A/D conversion halted), the conversion result of the A/D converter is indeterminate. The
contents of A/D register i irrelevant to A/D conversion may also become indeterminate. If while A/D
conversion is underway the ADST bit is cleared to “0” in a program, ignore the values of all A/D register
i.
program in single sweep conversion mode, A/D delayed trigger mode 0 and A/D delayed trigger mode
1 during A/D conversion operation, the A/D interrupt request may be generated. If this causes a prob-
lem, set the ADST bit to "0" after the interrupt is disabled.
2
A
• When operating in one-shot mode, single-sweep mode, simultaneous sample sweep mode, delayed
• When operating in repeat mode or repeat sweep mode 0 or 1
0
F
2
trigger mode 0 or delayed trigger mode 1
Check to see that A/D conversion is completed before reading the target A/D register i. (Check the IR
bit in the ADIC register to see if A/D conversion is completed.)
Use the main clock for CPU clock directly without dividing it.
e
G
0 -
b
o r
1 .
2
0
u
, 5
0
p
2
(
0
M
0
7
1
6
C
page 316
2 /
6
, A
M
1
f o
6
C
3
2
2 /
9
6
, B
M
1
6
C
2 /
6
) T
19. Usage Notes