HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 103

• Manufacturer Part Number: HD64F3048BF25
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048BF25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit 2—NMI Edge Select (NMIEG): Selects the valid edge of the NMI input.
Bit 1—Reserved: Read-only bit, always read as 1.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized by the rising edge of the RES signal. It is not initialized in software standby mode.
3.4
3.4.1
Ports 1, 2, and 5 function as address pins A
address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least
one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
3.4.2
Ports 1, 2, and 5 function as address pins A
address space. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all
areas are designated for 8-bit access in ABWCR, the bus mode switches to 8 bits.
3.4.3
Ports 1, 2, and 5 and part of port A function as address pins A
maximum 16-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to
all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to
16 bits. A
(BRCR). (In this mode A
Bit 2: NMIEG
0
1
Bit 0: RAME
0
1
23
Mode 1
Mode 2
Mode 3
Operating Mode Descriptions
to A
21
are valid when 0 is written in bits 7 to 5 of the bus release control register
Description
An interrupt is requested at the falling edge of NMI
An interrupt is requested at the rising edge of NMI
Description
On-chip RAM is disabled
On-chip RAM is enabled
20
is always used for address output.)
19
19
to A
to A
0
0
, permitting access to a maximum 1-Mbyte
, permitting access to a maximum 1-Mbyte
Rev. 3.00 Sep 27, 2006 page 75 of 872
23
to A
Section 3 MCU Operating Modes
0
, permitting access to a
REJ09B0325-0300
(Initial value)
(Initial value)