HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 535

• Manufacturer Part Number: HD64F3048BF25
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048BF25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Note: When switching from transmitting or receiving to simultaneous
No
No
No
transmitting and receiving, clear both the TE bit and the RE bit
to 0, then set both bits to 1.
Clear TE and RE bits to 0 in SCR
and clear RDRF flag to 0 in SSR
Start transmitting and receiving
Write transmit data in TDR and
Read receive data from RDR
clear TDRE flag to 0 in SSR
Read ORER flag in SSR
Read RDRF flag in SSR
Read TDRE flag in SSR
End of transmitting and
Figure 13.20 Sample Flowchart for Serial Transmitting
ORER = 1?
RDRF = 1?
TDRE = 1?
receiving?
Initialize
End
Yes
No
Yes
Yes
Error handling
Yes
1
2
4
5
3
Section 13 Serial Communication Interface
Rev. 3.00 Sep 27, 2006 page 507 of 872
1.
2.
3.
4.
5.
SCI initialization: the transmit data
output function of the TxD pin and
receive data input function of the
RxD pin are selected, enabling
simultaneous transmitting and
receiving.
SCI status check and transmit
data write: read SSR, check that
the TDRE flag is 1, then write
transmit data in TDR and clear
the TDRE flag to 0.
Notification that the TDRE flag has
changed from 0 to 1 can also be
given by the TXI interrupt.
Receive error handling: if a receive
error occurs, read the ORER flag in
SSR, then after executing the neces-
sary error handling, clear the ORER
flag to 0.
Neither transmitting nor receiving
can resume while the ORER flag
remains set to 1.
SCI status check and receive
data read: read SSR, check that
the RDRF flag is 1, then read
receive data from RDR and clear
the RDRF flag to 0. Notification
that the RDRF flag has changed
from 0 to 1 can also be given
by the RXI interrupt.
To continue transmitting and
receiving serial data: check the
RDRF flag, read RDR, and clear
the RDRF flag to 0 before the
MSB (bit 7) of the current frame
is received. Also check that
the TDRE flag is set to 1, indicat-
ing that data can be written, write
data in TDR, then clear the TDRE
flag to 0 before the MSB (bit 7) of
the current frame is transmitted.
When the DMAC is activated by
a transmit-data-empty interrupt
request (TXI) to write data in TDR,
the TDRE flag is checked and
cleared automatically. When the
DMAC is activated by a receive-
data-full interrupt request (RXI) to
read RDR, the RDRF flag is
cleared automatically.
REJ09B0325-0300