HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 342
HD64F3048BF25
Manufacturer Part Number
HD64F3048BF25
Description
IC H8 MCU FLASH 128K 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.DF3048BF25V.pdf
(903 pages)
Specifications of HD64F3048BF25
Core Processor
H8/300H
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3048BF25
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD64F3048BF25V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 342 of 903
- Download datasheet (5Mb)
Section 9 I/O Ports
Pin
PB
DREQ
CS
PB
TOCXB
PB
TOCXA
Rev. 3.00 Sep 27, 2006 page 314 of 872
REJ09B0325-0300
6
5
4
7
/TP
/TP
/TP
0
/
14
13
12
4
4
/
/
/
Pin Functions and Selection Method
Bit CS7E in CSCR, DMAC channel 0 settings (bits DTS2A to DTS0A and DTS2B to
DTS0B in DTCR0A and DTCR0B), bit NDER14 in NDERB, and bit PB
select the pin function as follows
PB
CS7E
NDER14
Pin function
Note:
DMAC
channel 0
settings
DTS2A, DTS1A
DTS0A
DTS2B
DTS1B
ITU channel 4 settings (bit CMD1 in TFCR and bit EXB4 in TOER), bit NDER13 in
NDERB, and bit PB
EXB4, CMD1
PB
NDER13
Pin function
ITU channel 4 settings (bit CMD1 in TFCR and bit EXA4 in TOER), bit NDER12 in
NDERB, and bit PB
EXA4, CMD1
PB
NDER12
Pin function
6
5
4
DDR
DDR
DDR
* DREQ
0
input under DMAC channel 0 settings (1) in the table below.
5
4
DDR in PBDDR select the pin function as follows
DDR in PBDDR select the pin function as follows
—
0
PB
PB
PB
6
5
4
(2)
—
—
—
Not both 1
0
0
0
0
input
input
input
—
1
0
DREQ
(1)
PB
PB
PB
Not both 1
Not both 1
1
1
6
5
4
output
output
output
1
0
0
1
0
1
0
0
input *
(2)
—
0
0
(1)
TP
—
TP
TP
0
1
14
13
12
output
output
output
1
0
1
1
1
1
1
Both 1
—
1
0
(2)
6
DDR in PBDDR
TOCXB
TOCXA
CS
1
1
0
Both 1
Both 1
7
—
—
—
—
—
—
—
output
1
4
4
output
output
(1)
1
1
1
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