HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 19

• Manufacturer Part Number: HD64F3048BF25
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048BF25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

8.2
8.3
8.4
8.5
8.6
Section 9 I/O Ports
9.1
8.1.3
8.1.4
8.1.5
Register Descriptions (Short Address Mode).................................................................... 205
8.2.1
8.2.2
8.2.3
8.2.4
Register Descriptions (Full Address Mode)...................................................................... 211
8.3.1
8.3.2
8.3.3
8.3.4
Operation .......................................................................................................................... 220
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.4.8
8.4.9
8.4.10 External Bus Requests, Refresh Controller, and DMAC ..................................... 248
8.4.11 NMI Interrupts and DMAC.................................................................................. 249
8.4.12 Aborting a DMA Transfer ................................................................................... 250
8.4.13 Exiting Full Address Mode.................................................................................. 251
8.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode ......................... 252
Interrupts ........................................................................................................................... 253
Usage Notes ...................................................................................................................... 254
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.6.6
8.6.7
8.6.8
Overview........................................................................................................................... 259
Functional Overview............................................................................................ 201
Input/Output Pins ................................................................................................. 203
Register Configuration......................................................................................... 203
Memory Address Registers (MAR) ..................................................................... 205
I/O Address Registers (IOAR) ............................................................................. 206
Execute Transfer Count Registers (ETCR).......................................................... 206
Data Transfer Control Registers (DTCR) ............................................................ 208
Memory Address Registers (MAR) ..................................................................... 211
I/O Address Registers (IOAR) ............................................................................. 211
Execute Transfer Count Registers (ETCR).......................................................... 212
Data Transfer Control Registers (DTCR) ............................................................ 214
Overview.............................................................................................................. 220
I/O Mode.............................................................................................................. 222
Idle Mode............................................................................................................. 224
Repeat Mode ........................................................................................................ 227
Normal Mode....................................................................................................... 231
Block Transfer Mode ........................................................................................... 234
DMAC Activation................................................................................................ 239
DMAC Bus Cycle ................................................................................................ 241
DMAC Multiple-Channel Operation ................................................................... 247
Note on Word Data Transfer................................................................................ 254
DMAC Self-Access ............................................................................................. 254
Longword Access to Memory Address Registers ................................................ 254
Note on Full Address Mode Setup ....................................................................... 254
Note on Activating DMAC by Internal Interrupts ............................................... 254
NMI Interrupts and Block Transfer Mode ........................................................... 256
Memory and I/O Address Register Values .......................................................... 256
Bus Cycle when Transfer Is Aborted ................................................................... 257
.............................................................................................................. 259
Rev. 3.00 Sep 27, 2006 page xvii of xxvi