HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 464

• Manufacturer Part Number: HD64F3048BF25
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048BF25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 11 Programmable Timing Pattern Controller
Example of Non-Overlapping TPC Output
(Example of Four-Phase Complementary Non-Overlapping Output)
Figure 11.7 shows an example of the use of TPC output for four-phase complementary non-
overlapping pulse output.
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GRB
GRA
H'0000
NDRB
PBDR
TP
TP
TP
TP
TP
TP
TP
TP
The output trigger ITU channel is set up so that GRA and GRB are output compare registers and the
counter will be cleared by compare match B. The TPC output trigger period is set in GRB. The non-
overlap margin is set in GRA. The IMIEA bit is set to 1 in TIER to enable IMFA interrupts.
H'FF is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set
in TPCR to select compare match in the ITU channel set up in step 1 as the output trigger.
Bits G3NOV and G2NOV are set to 1 in TPMR to select non-overlapping output. Output data H'95 is
written in NDRB.
The timer counter in this ITU channel is started. When compare match B occurs, outputs change from
1 to 0. When compare match A occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed
by the value of GRA). The IMFA interrupt service routine writes the next output data (H'65) in NDRB.
Four-phase complementary non-overlapping pulse output can be obtained by writing H'59, H'56, H'95…
at successive IMFA interrupts. If the DMAC is set for activation by this interrupt, pulse output can be
obtained without loading the CPU.
15
14
13
12
11
10
9
8
TCNT value
(Four-Phase Complementary Non-Overlapping Pulse Output)
TCNT
Figure 11.7 Non-Overlapping TPC Output Example
95
00
95
65
05
Non-overlap margin
65
59
41
59
56
50
56
95
14
95
65
05
65
Time