HD64F3048BF25 Renesas Electronics America, HD64F3048BF25 Datasheet - Page 523

• Manufacturer Part Number: HD64F3048BF25
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048BF25

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

In transmitting serial data, the SCI operates as follows.
1. The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI
2. After loading the data from TDR into TSR, the SCI sets the TDRE flag to 1 and starts
3. The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI
Figure 13.11 shows an example of SCI transmit operation using a multiprocessor format.
recognizes that TDR contains new data, and loads this data from TDR into TSR.
transmitting. If the TIE bit in SCR is set to 1, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
a. Start bit: One 0 bit is output.
b. Transmit data: 7 or 8 bits are output, LSB first.
c. Multiprocessor bit: One multiprocessor bit (MPBT value) is output.
d. Stop bit: One or two 1 bits (stop bits) are output.
e. Mark state: Output of 1 bits continues until the start bit of the next transmit data.
loads data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next
frame. If the TDRE flag is 1, the SCI sets the TEND flag in SSR to 1, outputs the stop bit, then
continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a transmit-end
interrupt (TEI) is requested at this time.
TDRE
TEND
1
TXI
request
Start
bit
0
(8-Bit Data with Multiprocessor Bit and One Stop Bit)
Figure 13.11 Example of SCI Transmit Operation
TXI interrupt handler
writes data in TDR and
clears TDRE flag to 0
D0
D1
1 frame
Data
D7
0/1
Multi-
processor
bit
Stop
bit
TXI
request
1
Start
bit
0
Section 13 Serial Communication Interface
Rev. 3.00 Sep 27, 2006 page 495 of 872
D0
D1
Data
D7
0/1
Multi-
processor
bit
TEI request
Stop
bit
REJ09B0325-0300
1
Idle (mark)
state
1